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authorKever Yang <kever.yang@rock-chips.com>2014-11-13 16:11:49 +0800
committerHeiko Stuebner <heiko@sntech.de>2014-11-16 00:40:19 +0100
commit29e94468516cdf191ec839ee39f79e011817276d (patch)
treec262b61f1785452a305e66993c7a0cfc5c99fd59 /drivers/clk/rockchip
parent0132234160ae46d8bd4677e37adb0b4366e05b1e (diff)
downloadblackbird-op-linux-29e94468516cdf191ec839ee39f79e011817276d.tar.gz
blackbird-op-linux-29e94468516cdf191ec839ee39f79e011817276d.zip
clk: rockchip: fix clock select order for rk3288 usbphy480m_src
According to rk3288 trm, the mux selector locate at bit[12:11] of CRU_CLKSEL13_CON shows: 2'b00: select HOST0 USB pll clock (clk_otgphy1) 2'b01: select HOST1 USB pll clock (clk_otgphy2) 2'b10: select OTG USB pll clock (clk_otgphy0) The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3 - clk_otgphy0 -> USB PHY OTG - clk_otgphy1 -> USB PHY host0 - clk_otgphy2 -> USB PHY host1 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip')
-rw-r--r--drivers/clk/rockchip/clk-rk3288.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index f27cdae61fd5..174589c95e33 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -195,8 +195,8 @@ PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
-PNAME(mux_usbphy480m_p) = { "sclk_otgphy0", "sclk_otgphy1",
- "sclk_otgphy2" };
+PNAME(mux_usbphy480m_p) = { "sclk_otgphy1", "sclk_otgphy2",
+ "sclk_otgphy0" };
PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
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