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| author | Thierry Reding <treding@nvidia.com> | 2014-04-04 15:55:13 +0200 |
|---|---|---|
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2014-04-17 14:12:34 +0300 |
| commit | d0f02ce3b1685ef6ffe43692034599790f83e7ab (patch) | |
| tree | 08b7289a4e5db66417e3d1455577345f29114ed1 /drivers/clk/clk-twl6040.c | |
| parent | c9eaa447e77efe77b7fa4c953bd62de8297fd6c5 (diff) | |
| download | blackbird-op-linux-d0f02ce3b1685ef6ffe43692034599790f83e7ab.tar.gz blackbird-op-linux-d0f02ce3b1685ef6ffe43692034599790f83e7ab.zip | |
clk: tegra: Fix PLLE programming
PLLE has M, N and P divider shift and width parameters that differ from
the defaults. Furthermore, when clearing the M, N and P divider fields
the corresponding masks were never shifted, thereby clearing only the
lowest bits of the register. This lead to a situation where the PLLE
programming would only work if the register hadn't been touched before.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clk/clk-twl6040.c')
0 files changed, 0 insertions, 0 deletions
