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| author | Thor Thayer <tthayer@opensource.altera.com> | 2016-02-10 13:26:21 -0600 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2016-02-11 12:23:06 +0100 |
| commit | c3eea1942a16db52ebea0382bd5826f75b9b7e9b (patch) | |
| tree | 3dae0d37c04b9a015d76eca8d0491c147370b511 /crypto/eseqiv.c | |
| parent | 9bf4f005672073f6bae2edf84e6cb5c4fb16ffc6 (diff) | |
| download | blackbird-op-linux-c3eea1942a16db52ebea0382bd5826f75b9b7e9b.tar.gz blackbird-op-linux-c3eea1942a16db52ebea0382bd5826f75b9b7e9b.zip | |
EDAC, altera: Add Altera L2 cache and OCRAM support
Add L2 Cache and On-Chip RAM EDAC support for the Altera SoCs. The SDRAM
controller is using the Memory Controller model.
Each type of ECC is individually configurable.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: ijc+devicetree@hellion.org.uk
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-doc@vger.kernel.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: mark.rutland@arm.com
Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Link: http://lkml.kernel.org/r/1455132384-17108-1-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'crypto/eseqiv.c')
0 files changed, 0 insertions, 0 deletions
