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authorPhilipp Zabel <p.zabel@pengutronix.de>2017-05-19 16:05:51 +0200
committerPhilipp Zabel <p.zabel@pengutronix.de>2017-07-17 12:58:11 +0200
commit790cb4c7c9545953d22d3d425e49b36a711bae5b (patch)
tree33913a427dd96b884fa6786cebb74426fd6a5b8a /crypto/ecb.c
parent58dff39904c02199b80395dac2fa3dec0d8f3861 (diff)
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drm/imx: lock scanout transfers for consecutive bursts
Because of its shallow queues and limited reordering ability, the i.MX6Q memory controller likes AXI bursts of consecutive addresses a lot. To optimize memory access performance, lock the IPU scanout channels for a number of burst accesses each, before switching to the next channel. The burst size and length of a locked burst chain are chosen not to overshoot the stride. Enabling the 8-burst channel lock on a single 1920x1080@60Hz RGBx scanout (474 MiB/s of 64-byte IPU memory read accesses) reduces the reported memory controller busy cycles from 46% to below 28% on an otherwise idle i.MX6Q. Tested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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