diff options
| author | Vikas Shivappa <vikas.shivappa@linux.intel.com> | 2017-08-09 11:46:34 -0700 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2017-08-14 11:47:47 +0200 |
| commit | a9110b552d44fedbd1221eb0e5bde81da32d9350 (patch) | |
| tree | a39373754332e059048fc04f221a6e69d7d557ce /arch/x86/include | |
| parent | eda61c265f3656be8345fdf0334b3a77829437fc (diff) | |
| download | blackbird-op-linux-a9110b552d44fedbd1221eb0e5bde81da32d9350.tar.gz blackbird-op-linux-a9110b552d44fedbd1221eb0e5bde81da32d9350.zip | |
x86/intel_rdt: Modify the intel_pqr_state for better performance
Currently we have pqr_state and rdt_default_state which store the cached
CLOSID/RMIDs and the user configured cpu default values respectively. We
touch both of these during context switch. Put all of them in one
structure so that we can spare a cache line.
Reported-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Vikas Shivappa <vikas.shivappa@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: ravi.v.shankar@intel.com
Cc: tony.luck@intel.com
Cc: fenghua.yu@intel.com
Cc: peterz@infradead.org
Cc: eranian@google.com
Cc: sai.praneeth.prakhya@intel.com
Cc: ak@linux.intel.com
Cc: davidcc@google.com
Link: http://lkml.kernel.org/r/1502304395-7166-3-git-send-email-vikas.shivappa@linux.intel.com
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/intel_rdt_sched.h | 30 |
1 files changed, 17 insertions, 13 deletions
diff --git a/arch/x86/include/asm/intel_rdt_sched.h b/arch/x86/include/asm/intel_rdt_sched.h index 3badc0a87ef5..b4bbf8b21512 100644 --- a/arch/x86/include/asm/intel_rdt_sched.h +++ b/arch/x86/include/asm/intel_rdt_sched.h @@ -10,8 +10,10 @@ /** * struct intel_pqr_state - State cache for the PQR MSR - * @rmid: The cached Resource Monitoring ID - * @closid: The cached Class Of Service ID + * @cur_rmid: The cached Resource Monitoring ID + * @cur_closid: The cached Class Of Service ID + * @default_rmid: The user assigned Resource Monitoring ID + * @default_closid: The user assigned cached Class Of Service ID * * The upper 32 bits of IA32_PQR_ASSOC contain closid and the * lower 10 bits rmid. The update to IA32_PQR_ASSOC always @@ -22,12 +24,13 @@ * not change. */ struct intel_pqr_state { - u32 rmid; - u32 closid; + u32 cur_rmid; + u32 cur_closid; + u32 default_rmid; + u32 default_closid; }; DECLARE_PER_CPU(struct intel_pqr_state, pqr_state); -DECLARE_PER_CPU_READ_MOSTLY(struct intel_pqr_state, rdt_cpu_default); DECLARE_STATIC_KEY_FALSE(rdt_enable_key); DECLARE_STATIC_KEY_FALSE(rdt_alloc_enable_key); @@ -49,8 +52,9 @@ DECLARE_STATIC_KEY_FALSE(rdt_mon_enable_key); */ static void __intel_rdt_sched_in(void) { - struct intel_pqr_state newstate = this_cpu_read(rdt_cpu_default); - struct intel_pqr_state *curstate = this_cpu_ptr(&pqr_state); + struct intel_pqr_state *state = this_cpu_ptr(&pqr_state); + u32 closid = state->default_closid; + u32 rmid = state->default_rmid; /* * If this task has a closid/rmid assigned, use it. @@ -58,18 +62,18 @@ static void __intel_rdt_sched_in(void) */ if (static_branch_likely(&rdt_alloc_enable_key)) { if (current->closid) - newstate.closid = current->closid; + closid = current->closid; } if (static_branch_likely(&rdt_mon_enable_key)) { if (current->rmid) - newstate.rmid = current->rmid; + rmid = current->rmid; } - if (newstate.closid != curstate->closid || - newstate.rmid != curstate->rmid) { - *curstate = newstate; - wrmsr(IA32_PQR_ASSOC, newstate.rmid, newstate.closid); + if (closid != state->cur_closid || rmid != state->cur_rmid) { + state->cur_closid = closid; + state->cur_rmid = rmid; + wrmsr(IA32_PQR_ASSOC, rmid, closid); } } |
