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authorAlexander Graf <agraf@suse.de>2010-01-08 02:58:06 +0100
committerMarcelo Tosatti <mtosatti@redhat.com>2010-03-01 12:35:49 -0300
commit021ec9c69f8b7b20f46296cc76cc4cb341b25191 (patch)
tree304f086761e7c01fb412c8319b89ff8b6fb2dde7 /arch/powerpc/kvm/book3s_64_rmhandlers.S
parentbc90923e27908ef65aa8aaad2f234e18b5273c78 (diff)
downloadblackbird-op-linux-021ec9c69f8b7b20f46296cc76cc4cb341b25191.tar.gz
blackbird-op-linux-021ec9c69f8b7b20f46296cc76cc4cb341b25191.zip
KVM: PPC: Call SLB patching code in interrupt safe manner
Currently we're racy when doing the transition from IR=1 to IR=0, from the module memory entry code to the real mode SLB switching code. To work around that I took a look at the RTAS entry code which is faced with a similar problem and did the same thing: A small helper in linear mapped memory that does mtmsr with IR=0 and then RFIs info the actual handler. Thanks to that trick we can safely take page faults in the entry code and only need to be really wary of what to do as of the SLB switching part. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Avi Kivity <avi@redhat.com>
Diffstat (limited to 'arch/powerpc/kvm/book3s_64_rmhandlers.S')
-rw-r--r--arch/powerpc/kvm/book3s_64_rmhandlers.S18
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/powerpc/kvm/book3s_64_rmhandlers.S b/arch/powerpc/kvm/book3s_64_rmhandlers.S
index 9ad1c2645d6f..e7091c9459a8 100644
--- a/arch/powerpc/kvm/book3s_64_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_64_rmhandlers.S
@@ -140,6 +140,24 @@ kvmppc_handler_lowmem_trampoline:
blr
kvmppc_handler_lowmem_trampoline_end:
+/*
+ * Call a function in real mode
+ *
+ * Input Registers:
+ *
+ * R3 = function
+ * R4 = MSR
+ * R5 = CTR
+ *
+ */
+_GLOBAL(kvmppc_rmcall)
+ mtmsr r4 /* Disable relocation, so mtsrr
+ doesn't get interrupted */
+ mtctr r5
+ mtsrr0 r3
+ mtsrr1 r4
+ RFI
+
.global kvmppc_trampoline_lowmem
kvmppc_trampoline_lowmem:
.long kvmppc_handler_lowmem_trampoline - _stext
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