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| author | Paul Burton <paul.burton@imgtec.com> | 2017-08-12 19:49:42 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2017-08-30 00:57:28 +0200 |
| commit | 3c9b4166213d415afa09bf2be104074f3a1161c8 (patch) | |
| tree | 090628d88c17fe1458da3497a0ded39b922f11a4 /arch/mips/pci | |
| parent | e83f7e02af50c763ed9f953b565a4fbce6235fdf (diff) | |
| download | blackbird-op-linux-3c9b4166213d415afa09bf2be104074f3a1161c8.tar.gz blackbird-op-linux-3c9b4166213d415afa09bf2be104074f3a1161c8.zip | |
MIPS: CPS: Cluster support for topology functions
Modify the functions we use to read information about the topology of
the system (the number of cores, VPs & IOCUs that it contains) in order
to take into account multiple clusters, and provide a new function to
determine the number of clusters in the system.
Users of these functions are modified only such that they continue to
build successfully - having them actually handle multiple clusters is
left to further patches.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17016/
Patchwork: https://patchwork.linux-mips.org/patch/17218/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
| -rw-r--r-- | arch/mips/pci/pci-malta.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/pci/pci-malta.c b/arch/mips/pci/pci-malta.c index de97b8f1c5a8..88e625fb3a47 100644 --- a/arch/mips/pci/pci-malta.c +++ b/arch/mips/pci/pci-malta.c @@ -201,7 +201,7 @@ void __init mips_pcibios_init(void) msc_mem_resource.start = start & mask; msc_mem_resource.end = (start & mask) | ~mask; msc_controller.mem_offset = (start & mask) - (map & mask); - if (mips_cm_numiocu()) { + if (mips_cps_numiocu(0)) { write_gcr_reg0_base(start); write_gcr_reg0_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0); @@ -213,7 +213,7 @@ void __init mips_pcibios_init(void) msc_io_resource.end = (map & mask) | ~mask; msc_controller.io_offset = 0; ioport_resource.end = ~mask; - if (mips_cm_numiocu()) { + if (mips_cps_numiocu(0)) { write_gcr_reg1_base(start); write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0); |
