Merge tag 'soc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

SoC related changes for omaps for v3.18 merge window:

- PM changes to make the code easier to use on newer SoCs
- PM changes for newer SoCs suspend and resume and wake-up events
- Minor clean-up to remove dead Kconfig options

Note that these have a dependency to the fixes-v3.18-not-urgent
tag and is based on a commit in that series.

* tag 'soc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (514 commits)
  ARM: OMAP5+: Reuse OMAP4 PM code for OMAP5 and DRA7
  ARM: dts: OMAP3+: Add PRM interrupt
  ARM: omap: Remove stray ARCH_HAS_OPP references
  ARM: DRA7: Add hook in SoC initcalls to enable pm initialization
  ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization
  ARM: OMAP5 / DRA7: Enable CPU RET on suspend
  ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplug
  ARM: OMAP5 / DRA7: PM: Avoid all SAR saves
  ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomains
  ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default
  ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency
  ARM: OMAP5 / DRA7: PM: Update CPU context register offset
  ARM: AM437x: use pdata quirks for pinctrl information
  ARM: DRA7: use pdata quirks for pinctrl information
  ARM: OMAP5: use pdata quirks for pinctrl information
  ARM: OMAP4+: PM: Use only valid low power state for CPU hotplug
  ARM: OMAP4+: PM: use only valid low power state for suspend
  ARM: OMAP4+: PM: Make logic state programmable
  ARM: OMAP2+: powerdomain: introduce logic for finding valid power domain
  ARM: OMAP2+: powerdomain: pwrdm_for_each_clkdm iterate only valid clkdms
  ...

3 files changed, 13 insertions, 5 deletions

diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 6f4f739dad96..e6e97d2a5c9e 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -13,6 +13,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/asmmacro.h>
 #include <asm/cacheops.h>
+#include <asm/eva.h>
 #include <asm/mipsregs.h>
 #include <asm/mipsmtregs.h>
 #include <asm/pm.h>
@@ -166,6 +167,9 @@ dcache_done:
 1:	jal	mips_cps_core_init
 	 nop
 
+	/* Do any EVA initialization if necessary */
+	eva_init
+
 	/*
 	 * Boot any other VPEs within this core that should be online, and
 	 * deactivate this VPE if it should be offline.
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 14bf74b0f51c..b63f2482f288 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -558,7 +558,7 @@ static int mipspmu_get_irq(void)
 	if (mipspmu.irq >= 0) {
 		/* Request my own irq handler. */
 		err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,
-			IRQF_PERCPU | IRQF_NOBALANCING,
+			IRQF_PERCPU | IRQF_NOBALANCING | IRQF_NO_THREAD,
 			"mips_perf_pmu", NULL);
 		if (err) {
 			pr_warning("Unable to request IRQ%d for MIPS "
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 13b964fddc4a..25bb8400156d 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -113,15 +113,19 @@ trace_a_syscall:
 	move	s0, t2			# Save syscall pointer
 	move	a0, sp
 	/*
-	 * syscall number is in v0 unless we called syscall(__NR_###)
+	 * absolute syscall number is in v0 unless we called syscall(__NR_###)
 	 * where the real syscall number is in a0
 	 * note: NR_syscall is the first O32 syscall but the macro is
 	 * only defined when compiling with -mabi=32 (CONFIG_32BIT)
 	 * therefore __NR_O32_Linux is used (4000)
 	 */
-	addiu	a1, v0,  __NR_O32_Linux
-	bnez	v0, 1f /* __NR_syscall at offset 0 */
-	lw	a1, PT_R4(sp)
+	.set	push
+	.set	reorder
+	subu	t1, v0,  __NR_O32_Linux
+	move	a1, v0
+	bnez	t1, 1f /* __NR_syscall at offset 0 */
+	lw	a1, PT_R4(sp) /* Arg1 for __NR_syscall case */
+	.set	pop
 
 1:	jal	syscall_trace_enter