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| author | Gabor Juhos <juhosg@openwrt.org> | 2013-02-15 13:38:23 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2013-02-19 09:36:32 +0100 |
| commit | 0a5f3b1c9f20eb44142e3b37662de15c944f759d (patch) | |
| tree | 4449da00868b3878745c6e18e666ca03e59be2c0 /arch/mips/include/asm/mach-ath79 | |
| parent | e9c0d0aaa3a7a6e66135e8b44f3323143a635098 (diff) | |
| download | blackbird-op-linux-0a5f3b1c9f20eb44142e3b37662de15c944f759d.tar.gz blackbird-op-linux-0a5f3b1c9f20eb44142e3b37662de15c944f759d.zip | |
MIPS: ath79: add PCI controller registration code for the QCA955X SoCs
Add SoC specific PCI IRQ map, and register platform
devices for the two built-in PCIe RCs.
Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4951/
Signed-off-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch/mips/include/asm/mach-ath79')
| -rw-r--r-- | arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 47282120db1e..b7fa9d14d20f 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -94,6 +94,19 @@ #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) #define AR934X_SRIF_SIZE 0x1000 +#define QCA955X_PCI_MEM_BASE0 0x10000000 +#define QCA955X_PCI_MEM_BASE1 0x12000000 +#define QCA955X_PCI_MEM_SIZE 0x02000000 +#define QCA955X_PCI_CFG_BASE0 0x14000000 +#define QCA955X_PCI_CFG_BASE1 0x16000000 +#define QCA955X_PCI_CFG_SIZE 0x1000 +#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA955X_PCI_CRP_SIZE 0x1000 +#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA955X_PCI_CTRL_SIZE 0x100 + #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) #define QCA955X_WMAC_SIZE 0x20000 |
