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authorGreg Ungerer <gerg@uclinux.org>2012-07-15 21:42:47 +1000
committerGreg Ungerer <gerg@uclinux.org>2012-09-27 23:33:46 +1000
commit6a3a786d02172b34d0ffba6f80bd1150da51125d (patch)
tree30ea2e51ba71f9a2adf987d38cc015294a53300a /arch/m68k/platform
parent300b9ff609ca027b9964a453a8156e6fe0077cde (diff)
downloadblackbird-op-linux-6a3a786d02172b34d0ffba6f80bd1150da51125d.tar.gz
blackbird-op-linux-6a3a786d02172b34d0ffba6f80bd1150da51125d.zip
m68knommu: make ColdFire IMR and IPR register definitions absolute addresses
Make all definitions of the ColdFire Interrupt Mask and Pending registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/platform')
-rw-r--r--arch/m68k/platform/coldfire/intc.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/arch/m68k/platform/coldfire/intc.c b/arch/m68k/platform/coldfire/intc.c
index 5c0c150b4067..cce257420388 100644
--- a/arch/m68k/platform/coldfire/intc.c
+++ b/arch/m68k/platform/coldfire/intc.c
@@ -45,23 +45,23 @@ unsigned char mcf_irq2imr[NR_IRQS];
void mcf_setimr(int index)
{
u16 imr;
- imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
- __raw_writew(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
+ imr = __raw_readw(MCFSIM_IMR);
+ __raw_writew(imr | (0x1 << index), MCFSIM_IMR);
}
void mcf_clrimr(int index)
{
u16 imr;
- imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
- __raw_writew(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
+ imr = __raw_readw(MCFSIM_IMR);
+ __raw_writew(imr & ~(0x1 << index), MCFSIM_IMR);
}
void mcf_maskimr(unsigned int mask)
{
u16 imr;
- imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
+ imr = __raw_readw(MCFSIM_IMR);
imr |= mask;
- __raw_writew(imr, MCF_MBAR + MCFSIM_IMR);
+ __raw_writew(imr, MCFSIM_IMR);
}
#else
@@ -69,23 +69,23 @@ void mcf_maskimr(unsigned int mask)
void mcf_setimr(int index)
{
u32 imr;
- imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
- __raw_writel(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
+ imr = __raw_readl(MCFSIM_IMR);
+ __raw_writel(imr | (0x1 << index), MCFSIM_IMR);
}
void mcf_clrimr(int index)
{
u32 imr;
- imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
- __raw_writel(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
+ imr = __raw_readl(MCFSIM_IMR);
+ __raw_writel(imr & ~(0x1 << index), MCFSIM_IMR);
}
void mcf_maskimr(unsigned int mask)
{
u32 imr;
- imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
+ imr = __raw_readl(MCFSIM_IMR);
imr |= mask;
- __raw_writel(imr, MCF_MBAR + MCFSIM_IMR);
+ __raw_writel(imr, MCFSIM_IMR);
}
#endif
@@ -104,9 +104,9 @@ void mcf_autovector(int irq)
#ifdef MCFSIM_AVR
if ((irq >= EIRQ1) && (irq <= EIRQ7)) {
u8 avec;
- avec = __raw_readb(MCF_MBAR + MCFSIM_AVR);
+ avec = __raw_readb(MCFSIM_AVR);
avec |= (0x1 << (irq - EIRQ1 + 1));
- __raw_writeb(avec, MCF_MBAR + MCFSIM_AVR);
+ __raw_writeb(avec, MCFSIM_AVR);
}
#endif
}
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