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| author | Mike Frysinger <vapier@gentoo.org> | 2010-07-28 19:59:03 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-08-06 12:55:55 -0400 |
| commit | ba3f5973ce3eb7ef4894ccd3df78c5cb410b17cc (patch) | |
| tree | 45880a04101440fe731ab15bca490886aaf50754 /arch/blackfin/mach-bf548/include/mach/defBF547.h | |
| parent | ada091729e8737edc3d455681fda9f745cfd2b63 (diff) | |
| download | blackbird-op-linux-ba3f5973ce3eb7ef4894ccd3df78c5cb410b17cc.tar.gz blackbird-op-linux-ba3f5973ce3eb7ef4894ccd3df78c5cb410b17cc.zip | |
Blackfin: TWI: clean up the MMR names
The standard short name for control is CTL and not CTRL. Use TWI0_xxx
even on parts that only have one TWI bus to keep things simple. Drop
all the cdef helpers since the bus driver takes care of everything.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf548/include/mach/defBF547.h')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF547.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h index 72c343646b2a..3d131065f8e6 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF547.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h @@ -99,15 +99,15 @@ #define TWI1_REGBASE 0xffc02200 #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ -#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ +#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */ #define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ #define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ -#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ +#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */ #define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ #define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ #define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ #define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ -#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ +#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */ #define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ #define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ #define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ |
