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authorMark Rutland <mark.rutland@arm.com>2015-03-24 15:10:21 +0000
committerWill Deacon <will.deacon@arm.com>2015-03-24 15:13:58 +0000
commit0c20856c260236b96f54c452d38dbe1348ed34d2 (patch)
treeb55c273e2889304f54643ee4b90325e92fb4190c /arch/arm64
parentd5efd9cc9cf2e422d064c912c7d5d985f52c1b2c (diff)
downloadblackbird-op-linux-0c20856c260236b96f54c452d38dbe1348ed34d2.tar.gz
blackbird-op-linux-0c20856c260236b96f54c452d38dbe1348ed34d2.zip
arm64: head.S: ensure idmap_t0sz is visible
We write idmap_t0sz with SCTLR_EL1.{C,M} clear, but we only have the guarnatee that the kernel Image is clean, not invalid in the caches, and therefore we might read a stale value once the MMU is enabled. This patch ensures we invalidate the corresponding cacheline after the write as we do for all other data written before we set SCTLR_EL1.{C.M}, guaranteeing that the value will be visible later. We rely on the DSBs in __create_page_tables to complete the maintenance. Signed-off-by: Mark Rutland <mark.rutland@arm.com> CC: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/kernel/head.S5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index bbc474cd0ca8..19f915e8f6e0 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -414,7 +414,10 @@ __create_page_tables:
cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough?
b.ge 1f // .. then skip additional level
- str_l x5, idmap_t0sz, x6
+ adr_l x6, idmap_t0sz
+ str x5, [x6]
+ dmb sy
+ dc ivac, x6 // Invalidate potentially stale cache line
create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6
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