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| author | Andre Przywara <andre.przywara@arm.com> | 2014-11-14 15:54:11 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2014-11-25 15:56:42 +0000 |
| commit | 5afaa1fc1b320cec48affa7e6949f2493f875c12 (patch) | |
| tree | 6d7d20ce61c2939548c6b5105bc5130c4f7191ac /arch/arm64/kernel/cpu_errata.c | |
| parent | 301bcfac42897dbd1b0b3c1be49f24654a1bc49e (diff) | |
| download | blackbird-op-linux-5afaa1fc1b320cec48affa7e6949f2493f875c12.tar.gz blackbird-op-linux-5afaa1fc1b320cec48affa7e6949f2493f875c12.zip | |
arm64: add Cortex-A57 erratum 832075 workaround
The ARM erratum 832075 applies to certain revisions of Cortex-A57,
one of the workarounds is to change device loads into using
load-aquire semantics.
This is achieved using the alternatives framework.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/kernel/cpu_errata.c')
| -rw-r--r-- | arch/arm64/kernel/cpu_errata.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index e107ed2d66dc..30935d2da55a 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -24,6 +24,7 @@ #include <asm/cpufeature.h> #define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) +#define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) /* * Add a struct or another datatype to the union below if you need @@ -71,6 +72,12 @@ struct arm64_cpu_capabilities arm64_errata[] = { MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02), }, { + /* Cortex-A57 r0p0 - r1p2 */ + .desc = "ARM erratum 832075", + .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, + MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 0x12), + }, + { } }; |
