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authorVivek Gautam <vivek.gautam@codeaurora.org>2017-07-31 12:14:42 +0530
committerAndy Gross <andy.gross@linaro.org>2017-08-08 16:29:51 -0500
commit42bd05442eb65efa4574943999d0e9d78b5a8514 (patch)
tree4fffc2e6bfcceace26d22da631190c6d3f2882ac /arch/arm64/boot/dts/qcom
parent6785fa95fc3eb560cd51327128c928baf941dd98 (diff)
downloadblackbird-op-linux-42bd05442eb65efa4574943999d0e9d78b5a8514.tar.gz
blackbird-op-linux-42bd05442eb65efa4574943999d0e9d78b5a8514.zip
arm64: dts: msm8996: Add device node for qcom qmp-phy for usb
Adding required device node for USB3 QMP phy present on msm8996 chipset to enable support for the same. This phy provides super speed usb functionality for dwc3 controller on msm8996. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts/qcom')
-rw-r--r--arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi4
-rw-r--r--arch/arm64/boot/dts/qcom/msm8996.dtsi33
2 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 2f5569b67c12..562fa1a72c02 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -89,6 +89,10 @@
status = "okay";
};
+ phy@7410000 {
+ status = "okay";
+ };
+
phy@7411000 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 4b85e13e59df..0bcfd9f4fac2 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -556,6 +556,39 @@
};
};
+ phy@7410000 {
+ compatible = "qcom,msm8996-qmp-usb3-phy";
+ reg = <0x7410000 0x1c4>;
+ #clock-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_CLKREF_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref";
+
+ vdda-phy-supply = <&pm8994_l28>;
+ vdda-pll-supply = <&pm8994_l12>;
+
+ resets = <&gcc GCC_USB3_PHY_BCR>,
+ <&gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "phy", "common";
+ status = "disabled";
+
+ ssusb_phy_0: lane@7410200 {
+ reg = <0x7410200 0x200>,
+ <0x7410400 0x130>,
+ <0x7410600 0x1a8>;
+ #phy-cells = <0>;
+
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ };
+ };
+
hsusb_phy1: phy@7411000 {
compatible = "qcom,msm8996-qusb2-phy";
reg = <0x7411000 0x180>;
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