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authorAnton Vorontsov <avorontsov@mvista.com>2011-07-06 16:45:09 +0400
committerAnton Vorontsov <avorontsov@mvista.com>2011-07-07 18:48:38 +0400
commit93e85d8e902e1a4468c6ade5c6ec3dd3055a489f (patch)
treed6ee8fdc4609b35f7b903d9b1e8cb07f4abe12db /arch/arm/mach-ux500
parent00d2711d700ae77b5bb66ea7c73eaa2cf155fa97 (diff)
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ARM: cns3xxx: Add support for L2 Cache Controller
CNS3xxx SOCs have L310-compatible cache controller, so let's use it. With this patch benchmarking with 'gzip' shows that performance is doubled, and I'm still able to boot full-fledged userland over NFS (using PCIe NIC), so the support should be pretty robust. p.s. While CNS3xxx reports that it has PL310, it still needs to wait on cache line operations, so we should not select 'CACHE_PL310', which is a micro-optimization that removes these waits for v7 CPUs. Someday we'd better rename CACHE_PL310 Kconfig option into NO_CACHE_WAIT or something less ambiguous. Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
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