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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-12-30 17:36:49 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-12-30 17:36:49 -0800 |
| commit | 14a3c4ab0e58d143c7928c9eb2f2610205e13bf2 (patch) | |
| tree | 885992999d7a1a2fd3586efcf32ebcbcbc3a72aa /arch/arm/mach-pxa/include | |
| parent | 1af237a099a3b8ff56aa384f605c6a68af7bf288 (diff) | |
| parent | 47992cbdaef2f18a47871b2ed01ad27f568c8b73 (diff) | |
| download | blackbird-op-linux-14a3c4ab0e58d143c7928c9eb2f2610205e13bf2.tar.gz blackbird-op-linux-14a3c4ab0e58d143c7928c9eb2f2610205e13bf2.zip | |
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (407 commits)
[ARM] pxafb: add support for overlay1 and overlay2 as framebuffer devices
[ARM] pxafb: cleanup of the timing checking code
[ARM] pxafb: cleanup of the color format manipulation code
[ARM] pxafb: add palette format support for LCCR4_PAL_FOR_3
[ARM] pxafb: add support for FBIOPAN_DISPLAY by dma braching
[ARM] pxafb: allow pxafb_set_par() to start from arbitrary yoffset
[ARM] pxafb: allow video memory size to be configurable
[ARM] pxa: add document on the MFP design and how to use it
[ARM] sa1100_wdt: don't assume CLOCK_TICK_RATE to be a constant
[ARM] rtc-sa1100: don't assume CLOCK_TICK_RATE to be a constant
[ARM] pxa/tavorevb: update board support (smartpanel LCD + keypad)
[ARM] pxa: Update eseries defconfig
[ARM] 5352/1: add w90p910-plat config file
[ARM] s3c: S3C options should depend on PLAT_S3C
[ARM] mv78xx0: implement GPIO and GPIO interrupt support
[ARM] Kirkwood: implement GPIO and GPIO interrupt support
[ARM] Orion: share GPIO IRQ handling code
[ARM] Orion: share GPIO handling code
[ARM] s3c: define __io using the typesafe version
[ARM] S3C64XX: Ensure CPU_V6 is selected
...
Diffstat (limited to 'arch/arm/mach-pxa/include')
23 files changed, 536 insertions, 575 deletions
diff --git a/arch/arm/mach-pxa/include/mach/clkdev.h b/arch/arm/mach-pxa/include/mach/clkdev.h new file mode 100644 index 000000000000..04b37a89801c --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h index 955bfe606067..7804637a6df3 100644 --- a/arch/arm/mach-pxa/include/mach/dma.h +++ b/arch/arm/mach-pxa/include/mach/dma.h @@ -30,10 +30,6 @@ typedef enum { DMA_PRIO_LOW = 2 } pxa_dma_prio; -#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) -#define HAVE_ARCH_PCI_SET_DMA_MASK 1 -#endif - /* * DMA registration */ diff --git a/arch/arm/mach-pxa/include/mach/eseries-gpio.h b/arch/arm/mach-pxa/include/mach/eseries-gpio.h index 4c90b1310270..efbd2aa9ecec 100644 --- a/arch/arm/mach-pxa/include/mach/eseries-gpio.h +++ b/arch/arm/mach-pxa/include/mach/eseries-gpio.h @@ -43,8 +43,10 @@ #define GPIO_E800_PCMCIA_PWR1 73 /* e7xx IrDA power control */ -#define GPIO_E7XX_IR_ON 38 +#define GPIO_E7XX_IR_OFF 38 /* ASIC related GPIOs */ #define GPIO_ESERIES_TMIO_IRQ 5 +#define GPIO_ESERIES_TMIO_PCLR 19 +#define GPIO_ESERIES_TMIO_SUSPEND 45 #define GPIO_E800_ANGELX_IRQ 8 diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h index 42ee1956750e..099f54a41de4 100644 --- a/arch/arm/mach-pxa/include/mach/gumstix.h +++ b/arch/arm/mach-pxa/include/mach/gumstix.h @@ -94,3 +94,7 @@ has detected a cable insertion; driven low otherwise. */ #define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN) #define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN) #define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN) + +/* for expansion boards that can't be programatically detected */ +extern int am200_init(void); + diff --git a/arch/arm/mach-pxa/include/mach/h5000.h b/arch/arm/mach-pxa/include/mach/h5000.h new file mode 100644 index 000000000000..2a5ae3802787 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/h5000.h @@ -0,0 +1,113 @@ +/* + * Hardware definitions for HP iPAQ h5xxx Handheld Computers + * + * Copyright(20)02 Hewlett-Packard Company. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, + * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS + * FITNESS FOR ANY PARTICULAR PURPOSE. + * + * Author: Jamey Hicks + */ + +#ifndef __ASM_ARCH_H5000_H +#define __ASM_ARCH_H5000_H + +#include <mach/mfp-pxa25x.h> + +/* + * CPU GPIOs + */ + +#define H5000_GPIO_POWER_BUTTON (0) +#define H5000_GPIO_RESET_BUTTON_N (1) +#define H5000_GPIO_OPT_INT (2) +#define H5000_GPIO_BACKUP_POWER (3) +#define H5000_GPIO_ACTION_BUTTON (4) +#define H5000_GPIO_COM_DCD_SOMETHING (5) /* what is this really ? */ +/* 6 not connected */ +#define H5000_GPIO_RESET_BUTTON_AGAIN_N (7) /* connected to gpio 1 as well */ +/* 8 not connected */ +#define H5000_GPIO_RSO_N (9) /* reset output from max1702 which regulates 3.3 and 2.5 */ +#define H5000_GPIO_ASIC_INT_N (10) /* from companion asic */ +#define H5000_GPIO_BT_ENV_0 (11) /* to LMX9814, set to 1 according to regdump */ +/*(12) not connected */ +#define H5000_GPIO_BT_ENV_1 (13) /* to LMX9814, set to 1 according to regdump */ +#define H5000_GPIO_BT_WU (14) /* from LMX9814, Defined as HOST_WAKEUP in the LMX9820 data sheet */ +/*(15) is CS1# */ +/*(16) not connected */ +/*(17) not connected */ +/*(18) is pcmcia ready */ +/*(19) is dreq1 */ +/*(20) is dreq0 */ +#define H5000_GPIO_OE_RD_NWR (21) /* output enable on rd/nwr signal to companion asic */ +/*(22) is not connected */ +#define H5000_GPIO_OPT_SPI_CLK (23) /* to extension pack */ +#define H5000_GPIO_OPT_SPI_CS_N (24) /* to extension pack */ +#define H5000_GPIO_OPT_SPI_DOUT (25) /* to extension pack */ +#define H5000_GPIO_OPT_SPI_DIN (26) /* to extension pack */ +/*(27) not connected */ +#define H5000_GPIO_I2S_BITCLK (28) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_DATAOUT (29) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_DATAIN (30) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_LRCLK (31) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_SYSCLK (32) /* connected to AC97 codec */ +/*(33) is CS5# */ +#define H5000_GPIO_COM_RXD (34) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_CTS (35) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_DCD (36) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_DSR (37) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_RI (38) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_TXD (39) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_DTR (40) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_RTS (41) /* connected to cradle/cable connector */ + +#define H5000_GPIO_BT_RXD (42) /* connected to BT (LMX9814) */ +#define H5000_GPIO_BT_TXD (43) /* connected to BT (LMX9814) */ +#define H5000_GPIO_BT_CTS (44) /* connected to BT (LMX9814) */ +#define H5000_GPIO_BT_RTS (45) /* connected to BT (LMX9814) */ + +#define H5000_GPIO_IRDA_RXD (46) +#define H5000_GPIO_IRDA_TXD (47) + +#define H5000_GPIO_POE_N (48) /* used for pcmcia */ +#define H5000_GPIO_PWE_N (49) /* used for pcmcia */ +#define H5000_GPIO_PIOR_N (50) /* used for pcmcia */ +#define H5000_GPIO_PIOW_N (51) /* used for pcmcia */ +#define H5000_GPIO_PCE1_N (52) /* used for pcmcia */ +#define H5000_GPIO_PCE2_N (53) /* used for pcmcia */ +#define H5000_GPIO_PSKTSEL (54) /* used for pcmcia */ +#define H5000_GPIO_PREG_N (55) /* used for pcmcia */ +#define H5000_GPIO_PWAIT_N (56) /* used for pcmcia */ +#define H5000_GPIO_IOIS16_N (57) /* used for pcmcia */ + +#define H5000_GPIO_IRDA_SD (58) /* to hsdl3002 sd */ +/*(59) not connected */ +#define H5000_GPIO_POWER_SD_N (60) /* controls power to SD */ +#define H5000_GPIO_POWER_RS232_N (61) /* inverted FORCEON to rs232 transceiver */ +#define H5000_GPIO_POWER_ACCEL_N (62) /* controls power to accel */ +/*(63) is not connected */ +#define H5000_GPIO_OPT_NVRAM (64) /* controls power to expansion pack */ +#define H5000_GPIO_CHG_EN (65) /* to sc801 en */ +#define H5000_GPIO_USB_PULLUP (66) /* USB d+ pullup via 1.5K resistor */ +#define H5000_GPIO_BT_2V8_N (67) /* 2.8V used by bluetooth */ +#define H5000_GPIO_EXT_CHG_RATE (68) /* enables external charging rate */ +/*(69) is not connected */ +#define H5000_GPIO_CIR_RESET (70) /* consumer IR reset */ +#define H5000_GPIO_POWER_LIGHT_SENSOR_N (71) +#define H5000_GPIO_BT_M_RESET (72) +#define H5000_GPIO_STD_CHG_RATE (73) +#define H5000_GPIO_SD_WP_N (74) +#define H5000_GPIO_MOTOR_ON_N (75) /* external pullup on this */ +#define H5000_GPIO_HEADPHONE_DETECT (76) +#define H5000_GPIO_USB_CHG_RATE (77) /* select rate for charging via usb */ +/*(78) is CS2# */ +/*(79) is CS3# */ +/*(80) is CS4# */ + +#endif /* __ASM_ARCH_H5000_H */ diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index a582a6d9b92b..16ab79547dae 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h @@ -102,6 +102,9 @@ * PXA930 B0 0x69056835 0x5E643013 * PXA930 B1 0x69056837 0x7E643013 * PXA930 B2 0x69056838 0x8E643013 + * + * PXA935 A0 0x56056931 0x1E653013 + * PXA935 B0 0x56056936 0x6E653013 */ #ifdef CONFIG_PXA25x #define __cpu_is_pxa210(id) \ @@ -178,12 +181,22 @@ #define __cpu_is_pxa930(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ - _id == 0x683; \ + _id == 0x683; \ }) #else #define __cpu_is_pxa930(id) (0) #endif +#ifdef CONFIG_CPU_PXA935 +#define __cpu_is_pxa935(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x693; \ + }) +#else +#define __cpu_is_pxa935(id) (0) +#endif + #define cpu_is_pxa210() \ ({ \ __cpu_is_pxa210(read_cpuid_id()); \ @@ -204,8 +217,6 @@ __cpu_is_pxa25x(read_cpuid_id()); \ }) -extern int cpu_is_pxa26x(void); - #define cpu_is_pxa27x() \ ({ \ __cpu_is_pxa27x(read_cpuid_id()); \ @@ -232,6 +243,12 @@ extern int cpu_is_pxa26x(void); __cpu_is_pxa930(id); \ }) +#define cpu_is_pxa935() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa935(id); \ + }) + /* * CPUID Core Generation Bit * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x @@ -249,6 +266,12 @@ extern int cpu_is_pxa26x(void); _id == 0x3; \ }) +#define __cpu_is_pxa9xx(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x683 || _id == 0x693; \ + }) + #define cpu_is_pxa2xx() \ ({ \ __cpu_is_pxa2xx(read_cpuid_id()); \ @@ -259,32 +282,25 @@ extern int cpu_is_pxa26x(void); __cpu_is_pxa3xx(read_cpuid_id()); \ }) -/* - * Handy routine to set GPIO alternate functions - */ -extern int pxa_gpio_mode( int gpio_mode ); - -/* - * Return GPIO level, nonzero means high, zero is low - */ -extern int pxa_gpio_get_value(unsigned gpio); - -/* - * Set output GPIO level - */ -extern void pxa_gpio_set_value(unsigned gpio, int value); - +#define cpu_is_pxa9xx() \ + ({ \ + __cpu_is_pxa9xx(read_cpuid_id()); \ + }) /* * return current memory and LCD clock frequency in units of 10kHz */ extern unsigned int get_memclk_frequency_10khz(void); +/* return the clock tick rate of the OS timer */ +extern unsigned long get_clock_tick_rate(void); #endif #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) #define PCIBIOS_MIN_IO 0 #define PCIBIOS_MIN_MEM 0 #define pcibios_assign_all_busses() 1 +#define HAVE_ARCH_PCI_SET_DMA_MASK 1 #endif + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h index 600fd4f76603..262691fb97d8 100644 --- a/arch/arm/mach-pxa/include/mach/io.h +++ b/arch/arm/mach-pxa/include/mach/io.h @@ -6,15 +6,13 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#include <mach/hardware.h> - #define IO_SPACE_LIMIT 0xffffffff /* * We don't actually have real ISA nor PCI buses, but there is so many * drivers out there that might just work if we fake them... */ -#define __io(a) ((void __iomem *)(a)) -#define __mem_pci(a) (a) +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) #endif diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h index 5c4e320c1437..6c9b21c51322 100644 --- a/arch/arm/mach-pxa/include/mach/littleton.h +++ b/arch/arm/mach-pxa/include/mach/littleton.h @@ -1,8 +1,13 @@ -#ifndef __ASM_ARCH_ZYLONITE_H -#define __ASM_ARCH_ZYLONITE_H +#ifndef __ASM_ARCH_LITTLETON_H +#define __ASM_ARCH_LITTLETON_H + +#include <mach/gpio.h> #define LITTLETON_ETH_PHYS 0x30000000 #define LITTLETON_GPIO_LCD_CS (17) -#endif /* __ASM_ARCH_ZYLONITE_H */ +#define EXT0_GPIO_BASE (NR_BUILTIN_GPIO) +#define EXT0_GPIO(x) (EXT0_GPIO_BASE + (x)) + +#endif /* __ASM_ARCH_LITTLETON_H */ diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h index 59aef89808d6..f626730ee42e 100644 --- a/arch/arm/mach-pxa/include/mach/memory.h +++ b/arch/arm/mach-pxa/include/mach/memory.h @@ -18,16 +18,6 @@ #define PHYS_OFFSET UL(0xa0000000) /* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - -/* * The nodes are matched with the physical SDRAM banks as follows: * * node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff @@ -47,6 +37,7 @@ void cmx2xx_pci_adjust_zones(int node, unsigned long *size, cmx2xx_pci_adjust_zones(node, size, holes) #define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) +#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) #endif #endif diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h index 617cab2cc8d0..a72869b73ee3 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h @@ -158,4 +158,35 @@ #define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) #define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) +#ifdef CONFIG_CPU_PXA26x +/* GPIO */ +#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) +#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF1) +#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF1) +#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF1) +#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF1) + +/* SDRAM */ +#define GPIO86_nSDCS2 MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH) +#define GPIO87_nSDCS3 MFP_CFG_OUT(GPIO87, AF0, DRIVE_HIGH) +#define GPIO88_RDnWR MFP_CFG_OUT(GPIO88, AF0, DRIVE_HIGH) +#define GPIO89_nACRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH) + +/* USB */ +#define GPIO9_USB_RCV MFP_CFG_IN(GPIO9, AF1) +#define GPIO32_USB_VP MFP_CFG_IN(GPIO32, AF2) +#define GPIO34_USB_VM MFP_CFG_IN(GPIO34, AF2) +#define GPIO39_USB_VPO MFP_CFG_OUT(GPIO39, AF3, DRIVE_LOW) +#define GPIO56_USB_VMO MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW) +#define GPIO57_USB_nOE MFP_CFG_OUT(GPIO57, AF1, DRIVE_HIGH) + +/* ASSP */ +#define GPIO28_ASSP_BITCLK_IN MFP_CFG_IN(GPIO28, AF3) +#define GPIO28_ASSP_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF3, DRIVE_LOW) +#define GPIO29_ASSP_RXD MFP_CFG_IN(GPIO29, AF3) +#define GPIO30_ASSP_TXD MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW) +#define GPIO31_ASSP_SFRM_IN MFP_CFG_IN(GPIO31, AF1) +#define GPIO31_ASSP_SFRM_OUT MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW) +#endif + #endif /* __ASM_ARCH_MFP_PXA25X_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h index 122bdbd53182..da4f85a4f990 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h @@ -11,6 +11,12 @@ #include <mach/mfp.h> #include <mach/mfp-pxa2xx.h> +/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN + * bit is set, regardless of the GPIO configuration + */ +#define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0) +#define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0) + /* GPIO */ #define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) #define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0) diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h index fabd9b4df827..fa73f56a1372 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h @@ -421,6 +421,7 @@ #define GPIO20_PWM0 MFP_CFG_LPM(GPIO20, AF2, PULL_LOW) #define GPIO21_PWM2 MFP_CFG_LPM(GPIO21, AF3, PULL_LOW) #define GPIO22_PWM3 MFP_CFG_LPM(GPIO22, AF3, PULL_LOW) +#define GPIO32_PWM0 MFP_CFG_LPM(GPIO32, AF4, PULL_LOW) /* CIR */ #define GPIO46_CIR_OUT MFP_CFG(GPIO46, AF1) diff --git a/arch/arm/mach-pxa/include/mach/mioa701.h b/arch/arm/mach-pxa/include/mach/mioa701.h index 8483cb511831..02868447b0b1 100644 --- a/arch/arm/mach-pxa/include/mach/mioa701.h +++ b/arch/arm/mach-pxa/include/mach/mioa701.h @@ -10,12 +10,14 @@ (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) /* Global GPIOs */ -#define GPIO9_CHARGE_nEN 9 +#define GPIO9_CHARGE_EN 9 #define GPIO18_POWEROFF 18 #define GPIO87_LCD_POWER 87 +#define GPIO96_AC_DETECT 96 +#define GPIO80_MAYBE_CHARGE_VDROP 80 /* Drop of 88mV */ /* USB */ -#define GPIO13_USB_DETECT 13 +#define GPIO13_nUSB_DETECT 13 #define GPIO22_USB_ENABLE 22 /* SDIO bits */ @@ -24,7 +26,10 @@ #define GPIO91_SDIO_EN 91 /* Bluetooth */ +#define GPIO14_BT_nACTIVITY 14 #define GPIO83_BT_ON 83 +#define GPIO77_BT_UNKNOWN1 77 +#define GPIO86_BT_MAYBE_nRESET 86 /* GPS */ #define GPIO23_GPS_UNKNOWN1 23 diff --git a/arch/arm/mach-pxa/include/mach/mtd-xip.h b/arch/arm/mach-pxa/include/mach/mtd-xip.h index 4d452fcb1508..cfca8155be72 100644 --- a/arch/arm/mach-pxa/include/mach/mtd-xip.h +++ b/arch/arm/mach-pxa/include/mach/mtd-xip.h @@ -15,6 +15,7 @@ #ifndef __ARCH_PXA_MTD_XIP_H__ #define __ARCH_PXA_MTD_XIP_H__ +#include <mach/hardware.h> #include <mach/pxa-regs.h> #define xip_irqpending() (ICIP & ICMR) diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h index 15295d960000..31d615aa7723 100644 --- a/arch/arm/mach-pxa/include/mach/pxa-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h @@ -13,6 +13,7 @@ #ifndef __PXA_REGS_H #define __PXA_REGS_H +#include <mach/hardware.h> /* * PXA Chip selects @@ -123,298 +124,6 @@ #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ - -/* - * UARTs - */ - -/* Full Function UART (FFUART) */ -#define FFUART FFRBR -#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ -#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ -#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ -#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ -#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ -#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ -#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ -#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ -#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ -#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ -#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ -#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -/* Bluetooth UART (BTUART) */ -#define BTUART BTRBR -#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ -#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ -#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ -#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ -#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ -#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ -#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ -#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ -#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ -#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ -#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ -#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -/* Standard UART (STUART) */ -#define STUART STRBR -#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ -#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ -#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ -#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ -#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ -#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ -#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ -#define STLSR __REG(0x40700014) /* Line Status Register (read only) */ -#define STMSR __REG(0x40700018) /* Reserved */ -#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ -#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ -#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -/* Hardware UART (HWUART) */ -#define HWUART HWRBR -#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ -#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ -#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ -#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ -#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ -#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ -#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ -#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ -#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ -#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ -#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ -#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ -#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ -#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ -#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -#define IER_DMAE (1 << 7) /* DMA Requests Enable */ -#define IER_UUE (1 << 6) /* UART Unit Enable */ -#define IER_NRZE (1 << 5) /* NRZ coding Enable */ -#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ -#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ -#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ -#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ -#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ - -#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ -#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ -#define IIR_TOD (1 << 3) /* Time Out Detected */ -#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ -#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ -#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ - -#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ -#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ -#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ -#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ -#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ -#define FCR_ITL_1 (0) -#define FCR_ITL_8 (FCR_ITL1) -#define FCR_ITL_16 (FCR_ITL2) -#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) - -#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ -#define LCR_SB (1 << 6) /* Set Break */ -#define LCR_STKYP (1 << 5) /* Sticky Parity */ -#define LCR_EPS (1 << 4) /* Even Parity Select */ -#define LCR_PEN (1 << 3) /* Parity Enable */ -#define LCR_STB (1 << 2) /* Stop Bit */ -#define LCR_WLS1 (1 << 1) /* Word Length Select */ -#define LCR_WLS0 (1 << 0) /* Word Length Select */ - -#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ -#define LSR_TEMT (1 << 6) /* Transmitter Empty */ -#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ -#define LSR_BI (1 << 4) /* Break Interrupt */ -#define LSR_FE (1 << 3) /* Framing Error */ -#define LSR_PE (1 << 2) /* Parity Error */ -#define LSR_OE (1 << 1) /* Overrun Error */ -#define LSR_DR (1 << 0) /* Data Ready */ - -#define MCR_LOOP (1 << 4) -#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ -#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ -#define MCR_RTS (1 << 1) /* Request to Send */ -#define MCR_DTR (1 << 0) /* Data Terminal Ready */ - -#define MSR_DCD (1 << 7) /* Data Carrier Detect */ -#define MSR_RI (1 << 6) /* Ring Indicator */ -#define MSR_DSR (1 << 5) /* Data Set Ready */ -#define MSR_CTS (1 << 4) /* Clear To Send */ -#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ -#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ -#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ -#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ - -/* - * IrSR (Infrared Selection Register) - */ -#define STISR_RXPL (1 << 4) /* Receive Data Polarity */ -#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ -#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ -#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ -#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ - - -/* - * I2C registers - moved into drivers/i2c/busses/i2c-pxa.c - */ - -/* - * Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c - */ - -/* - * AC97 Controller registers - */ - -#define POCR __REG(0x40500000) /* PCM Out Control Register */ -#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define PICR __REG(0x40500004) /* PCM In Control Register */ -#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define MCCR __REG(0x40500008) /* Mic In Control Register */ -#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define GCR __REG(0x4050000C) /* Global Control Register */ -#ifdef CONFIG_PXA3xx -#define GCR_CLKBPB (1 << 31) /* Internal clock enable */ -#endif -#define GCR_nDMAEN (1 << 24) /* non DMA Enable */ -#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ -#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ -#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ -#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ -#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ -#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ -#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ -#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ -#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ -#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ - -#define POSR __REG(0x40500010) /* PCM Out Status Register */ -#define POSR_FIFOE (1 << 4) /* FIFO error */ -#define POSR_FSR (1 << 2) /* FIFO Service Request */ - -#define PISR __REG(0x40500014) /* PCM In Status Register */ -#define PISR_FIFOE (1 << 4) /* FIFO error */ -#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ -#define PISR_FSR (1 << 2) /* FIFO Service Request */ - -#define MCSR __REG(0x40500018) /* Mic In Status Register */ -#define MCSR_FIFOE (1 << 4) /* FIFO error */ -#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ -#define MCSR_FSR (1 << 2) /* FIFO Service Request */ - -#define GSR __REG(0x4050001C) /* Global Status Register */ -#define GSR_CDONE (1 << 19) /* Command Done */ -#define GSR_SDONE (1 << 18) /* Status Done */ -#define GSR_RDCS (1 << 15) /* Read Completion Status */ -#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ -#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ -#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ -#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ -#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ -#define GSR_SCR (1 << 9) /* Secondary Codec Ready */ -#define GSR_PCR (1 << 8) /* Primary Codec Ready */ -#define GSR_MCINT (1 << 7) /* Mic In Interrupt */ -#define GSR_POINT (1 << 6) /* PCM Out Interrupt */ -#define GSR_PIINT (1 << 5) /* PCM In Interrupt */ -#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ -#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ -#define GSR_MIINT (1 << 1) /* Modem In Interrupt */ -#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ - -#define CAR __REG(0x40500020) /* CODEC Access Register */ -#define CAR_CAIP (1 << 0) /* Codec Access In Progress */ - -#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ -#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ - -#define MOCR __REG(0x40500100) /* Modem Out Control Register */ -#define MOCR_FEIE (1 << 3) /* FIFO Error */ -#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define MICR __REG(0x40500108) /* Modem In Control Register */ -#define MICR_FEIE (1 << 3) /* FIFO Error */ -#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define MOSR __REG(0x40500110) /* Modem Out Status Register */ -#define MOSR_FIFOE (1 << 4) /* FIFO error */ -#define MOSR_FSR (1 << 2) /* FIFO Service Request */ - -#define MISR __REG(0x40500118) /* Modem In Status Register */ -#define MISR_FIFOE (1 << 4) /* FIFO error */ -#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ -#define MISR_FSR (1 << 2) /* FIFO Service Request */ - -#define MODR __REG(0x40500140) /* Modem FIFO Data Register */ - -#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ -#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ -#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ -#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ - - -/* - * Fast Infrared Communication Port - */ - -#define FICP __REG(0x40800000) /* Start of FICP area */ -#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ -#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ -#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ -#define ICDR __REG(0x4080000c) /* ICP Data Register */ -#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ -#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ - -#define ICCR0_AME (1 << 7) /* Address match enable */ -#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ -#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ -#define ICCR0_RXE (1 << 4) /* Receive enable */ -#define ICCR0_TXE (1 << 3) /* Transmit enable */ -#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */ -#define ICCR0_LBM (1 << 1) /* Loopback mode */ -#define ICCR0_ITR (1 << 0) /* IrDA transmission */ - -#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ -#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ -#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ -#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ -#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ -#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ - -#ifdef CONFIG_PXA27x -#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ -#endif -#define ICSR0_FRE (1 << 5) /* Framing error */ -#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */ -#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */ -#define ICSR0_RAB (1 << 2) /* Receiver abort */ -#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */ -#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */ - -#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */ -#define ICSR1_CRE (1 << 5) /* CRC error */ -#define ICSR1_EOF (1 << 4) /* End of frame */ -#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */ -#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */ -#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */ -#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */ - - /* * Real Time Clock */ @@ -463,19 +172,6 @@ /* - * Pulse Width Modulator - */ - -#define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */ -#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */ -#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */ - -#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */ -#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */ -#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */ - - -/* * Interrupt Controller */ @@ -496,19 +192,6 @@ * General Purpose I/O */ -#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) -#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) -#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) -#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) - -#define GPLR_OFFSET 0x00 -#define GPDR_OFFSET 0x0C -#define GPSR_OFFSET 0x18 -#define GPCR_OFFSET 0x24 -#define GRER_OFFSET 0x30 -#define GFER_OFFSET 0x3C -#define GEDR_OFFSET 0x48 - #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ @@ -558,10 +241,6 @@ #define GPIO_bit(x) (1 << ((x) & 0x1f)) -#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) - -/* Interrupt Controller */ - #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) @@ -580,189 +259,5 @@ #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) -#else - -#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) -#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) -#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) -#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) -#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) -#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) -#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) -#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) - -#endif - -/* - * Power Manager - see pxa2xx-regs.h - */ - -/* - * SSP Serial Port Registers - see arch/arm/mach-pxa/include/mach/regs-ssp.h - */ - -/* - * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h - */ - -/* - * Core Clock - see arch/arm/mach-pxa/include/mach/pxa2xx-regs.h - */ - -#ifdef CONFIG_PXA27x - -/* Camera Interface */ -#define CICR0 __REG(0x50000000) -#define CICR1 __REG(0x50000004) -#define CICR2 __REG(0x50000008) -#define CICR3 __REG(0x5000000C) -#define CICR4 __REG(0x50000010) -#define CISR __REG(0x50000014) -#define CIFR __REG(0x50000018) -#define CITOR __REG(0x5000001C) -#define CIBR0 __REG(0x50000028) -#define CIBR1 __REG(0x50000030) -#define CIBR2 __REG(0x50000038) - -#define CICR0_DMAEN (1 << 31) /* DMA request enable */ -#define CICR0_PAR_EN (1 << 30) /* Parity enable */ -#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ -#define CICR0_ENB (1 << 28) /* Camera interface enable */ -#define CICR0_DIS (1 << 27) /* Camera interface disable */ -#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ -#define CICR0_TOM (1 << 9) /* Time-out mask */ -#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ -#define CICR0_FEM (1 << 7) /* FIFO-empty mask */ -#define CICR0_EOLM (1 << 6) /* End-of-line mask */ -#define CICR0_PERRM (1 << 5) /* Parity-error mask */ -#define CICR0_QDM (1 << 4) /* Quick-disable mask */ -#define CICR0_CDM (1 << 3) /* Disable-done mask */ -#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ -#define CICR0_EOFM (1 << 1) /* End-of-frame mask */ -#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ - -#define CICR1_TBIT (1 << 31) /* Transparency bit */ -#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ -#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ -#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ -#define CICR1_RGB_F (1 << 11) /* RGB format */ -#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ -#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ -#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ -#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ -#define CICR1_DW (0x7 << 0) /* Data width mask */ - -#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock - wait count mask */ -#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock - wait count mask */ -#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ -#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock - wait count mask */ -#define CICR2_FSW (0x7 << 0) /* Frame stabilization - wait count mask */ - -#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock - wait count mask */ -#define CICR3_EFW (0xff << 16) /* End-of-frame line clock - wait count mask */ -#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ -#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock - wait count mask */ -#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ - -#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ -#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ -#define CICR4_PCP (1 << 22) /* Pixel clock polarity */ -#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ -#define CICR4_VSP (1 << 20) /* Vertical sync polarity */ -#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ -#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ -#define CICR4_DIV (0xff << 0) /* Clock divisor mask */ - -#define CISR_FTO (1 << 15) /* FIFO time-out */ -#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ -#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ -#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ -#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ -#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ -#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ -#define CISR_EOL (1 << 8) /* End of line */ -#define CISR_PAR_ERR (1 << 7) /* Parity error */ -#define CISR_CQD (1 << 6) /* Camera interface quick disable */ -#define CISR_CDD (1 << 5) /* Camera interface disable done */ -#define CISR_SOF (1 << 4) /* Start of frame */ -#define CISR_EOF (1 << 3) /* End of frame */ -#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ -#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ -#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ - -#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ -#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ -#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ -#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ -#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ -#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ -#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ -#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ - -#define SRAM_SIZE 0x40000 /* 4x64K */ - -#define SRAM_MEM_PHYS 0x5C000000 - -#define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */ -#define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */ - -#define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */ -#define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */ -#define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */ -#define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */ - -#define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */ -#define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */ -#define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */ -#define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */ - -#define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */ -#define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */ -#define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */ -#define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */ - -#define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */ -#define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */ -#define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */ -#define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */ - -#define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */ -#define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */ -#define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */ -#define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */ - -#define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */ - -#define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */ -#define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */ -#define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */ - -#define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */ -#define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */ -#define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */ - -#define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */ -#define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */ -#define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */ - -#define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */ -#define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */ -#define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */ - -#endif - -/* PWRMODE register M field values */ - -#define PWRMODE_IDLE 0x1 -#define PWRMODE_STANDBY 0x2 -#define PWRMODE_SLEEP 0x3 -#define PWRMODE_DEEPSLEEP 0x7 #endif diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h index 6ef1dd09970b..d83393e25273 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h @@ -365,4 +365,9 @@ #define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN) #define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) +/* + * Handy routine to set GPIO alternate functions + */ +extern int pxa_gpio_mode( int gpio_mode ); + #endif /* __ASM_ARCH_PXA2XX_GPIO_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h index 806ecfea44bf..77102d695cc7 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h @@ -49,6 +49,11 @@ #define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ #define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ +#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */ +#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */ +#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */ +#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */ + #define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ @@ -243,4 +248,11 @@ #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ +/* PWRMODE register M field values */ + +#define PWRMODE_IDLE 0x1 +#define PWRMODE_STANDBY 0x2 +#define PWRMODE_SLEEP 0x3 +#define PWRMODE_DEEPSLEEP 0x7 + #endif diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h index cbda4d35c421..6932720ba04e 100644 --- a/arch/arm/mach-pxa/include/mach/pxafb.h +++ b/arch/arm/mach-pxa/include/mach/pxafb.h @@ -48,6 +48,7 @@ #define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN) #define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN) #define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN) +#define LCD_COLOR_TFT_8BPP ((8 << 4) | LCD_TYPE_COLOR_TFT) #define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT) #define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT) #define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL) @@ -94,6 +95,10 @@ struct pxafb_mode_info { * in pxa27x and pxa3xx, initialize them to the same value or * the larger one will be used * 3. same to {rd,wr}_pulse_width + * + * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity + * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0 + * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD */ unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */ unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */ @@ -108,6 +113,7 @@ struct pxafb_mach_info { unsigned int num_modes; unsigned int lcd_conn; + unsigned long video_mem_size; u_int fixed_modes:1, cmap_inverse:1, diff --git a/arch/arm/mach-pxa/include/mach/regs-ac97.h b/arch/arm/mach-pxa/include/mach/regs-ac97.h new file mode 100644 index 000000000000..e41b9d202b8c --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-ac97.h @@ -0,0 +1,99 @@ +#ifndef __ASM_ARCH_REGS_AC97_H +#define __ASM_ARCH_REGS_AC97_H + +/* + * AC97 Controller registers + */ + +#define POCR __REG(0x40500000) /* PCM Out Control Register */ +#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define PICR __REG(0x40500004) /* PCM In Control Register */ +#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define MCCR __REG(0x40500008) /* Mic In Control Register */ +#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define GCR __REG(0x4050000C) /* Global Control Register */ +#ifdef CONFIG_PXA3xx +#define GCR_CLKBPB (1 << 31) /* Internal clock enable */ +#endif +#define GCR_nDMAEN (1 << 24) /* non DMA Enable */ +#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ +#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ +#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ +#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ +#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ +#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ +#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ +#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ +#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ +#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ + +#define POSR __REG(0x40500010) /* PCM Out Status Register */ +#define POSR_FIFOE (1 << 4) /* FIFO error */ +#define POSR_FSR (1 << 2) /* FIFO Service Request */ + +#define PISR __REG(0x40500014) /* PCM In Status Register */ +#define PISR_FIFOE (1 << 4) /* FIFO error */ +#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ +#define PISR_FSR (1 << 2) /* FIFO Service Request */ + +#define MCSR __REG(0x40500018) /* Mic In Status Register */ +#define MCSR_FIFOE (1 << 4) /* FIFO error */ +#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ +#define MCSR_FSR (1 << 2) /* FIFO Service Request */ + +#define GSR __REG(0x4050001C) /* Global Status Register */ +#define GSR_CDONE (1 << 19) /* Command Done */ +#define GSR_SDONE (1 << 18) /* Status Done */ +#define GSR_RDCS (1 << 15) /* Read Completion Status */ +#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ +#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ +#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ +#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ +#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ +#define GSR_SCR (1 << 9) /* Secondary Codec Ready */ +#define GSR_PCR (1 << 8) /* Primary Codec Ready */ +#define GSR_MCINT (1 << 7) /* Mic In Interrupt */ +#define GSR_POINT (1 << 6) /* PCM Out Interrupt */ +#define GSR_PIINT (1 << 5) /* PCM In Interrupt */ +#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ +#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ +#define GSR_MIINT (1 << 1) /* Modem In Interrupt */ +#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ + +#define CAR __REG(0x40500020) /* CODEC Access Register */ +#define CAR_CAIP (1 << 0) /* Codec Access In Progress */ + +#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ +#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ + +#define MOCR __REG(0x40500100) /* Modem Out Control Register */ +#define MOCR_FEIE (1 << 3) /* FIFO Error */ +#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define MICR __REG(0x40500108) /* Modem In Control Register */ +#define MICR_FEIE (1 << 3) /* FIFO Error */ +#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define MOSR __REG(0x40500110) /* Modem Out Status Register */ +#define MOSR_FIFOE (1 << 4) /* FIFO error */ +#define MOSR_FSR (1 << 2) /* FIFO Service Request */ + +#define MISR __REG(0x40500118) /* Modem In Status Register */ +#define MISR_FIFOE (1 << 4) /* FIFO error */ +#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ +#define MISR_FSR (1 << 2) /* FIFO Service Request */ + +#define MODR __REG(0x40500140) /* Modem FIFO Data Register */ + +#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ +#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ +#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ +#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ + +#endif /* __ASM_ARCH_REGS_AC97_H */ diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h index c689c4ea769c..f82dcea792d9 100644 --- a/arch/arm/mach-pxa/include/mach/regs-lcd.h +++ b/arch/arm/mach-pxa/include/mach/regs-lcd.h @@ -12,27 +12,29 @@ #define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ #define LCCR4 (0x010) /* LCD Controller Control Register 4 */ #define LCCR5 (0x014) /* LCD Controller Control Register 5 */ -#define DFBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ -#define DFBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ -#define LCSR (0x038) /* LCD Controller Status Register */ +#define LCSR (0x038) /* LCD Controller Status Register 0 */ +#define LCSR1 (0x034) /* LCD Controller Status Register 1 */ #define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ #define TMEDRGBR (0x040) /* TMED RGB Seed Register */ #define TMEDCR (0x044) /* TMED Control Register */ +#define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ +#define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ +#define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */ +#define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */ +#define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */ +#define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */ +#define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */ + +#define OVL1C1 (0x050) /* Overlay 1 Control Register 1 */ +#define OVL1C2 (0x060) /* Overlay 1 Control Register 2 */ +#define OVL2C1 (0x070) /* Overlay 2 Control Register 1 */ +#define OVL2C2 (0x080) /* Overlay 2 Control Register 2 */ + #define CMDCR (0x100) /* Command Control Register */ #define PRSR (0x104) /* Panel Read Status Register */ -#define LCCR3_1BPP (0 << 24) -#define LCCR3_2BPP (1 << 24) -#define LCCR3_4BPP (2 << 24) -#define LCCR3_8BPP (3 << 24) -#define LCCR3_16BPP (4 << 24) -#define LCCR3_18BPP (5 << 24) -#define LCCR3_18BPP_P (6 << 24) -#define LCCR3_19BPP (7 << 24) -#define LCCR3_19BPP_P (1 << 29) -#define LCCR3_24BPP ((1 << 29) | (1 << 24)) -#define LCCR3_25BPP ((1 << 29) | (2 << 24)) +#define LCCR3_BPP(x) ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0)) #define LCCR3_PDFOR_0 (0 << 30) #define LCCR3_PDFOR_1 (1 << 30) @@ -42,19 +44,16 @@ #define LCCR4_PAL_FOR_0 (0 << 15) #define LCCR4_PAL_FOR_1 (1 << 15) #define LCCR4_PAL_FOR_2 (2 << 15) +#define LCCR4_PAL_FOR_3 (3 << 15) #define LCCR4_PAL_FOR_MASK (3 << 15) #define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */ -#define FSADR0 (0x204) /* DMA Channel 0 Frame Source Address Register */ -#define FIDR0 (0x208) /* DMA Channel 0 Frame ID Register */ -#define LDCMD0 (0x20C) /* DMA Channel 0 Command Register */ #define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */ -#define FSADR1 (0x214) /* DMA Channel 1 Frame Source Address Register */ -#define FIDR1 (0x218) /* DMA Channel 1 Frame ID Register */ -#define LDCMD1 (0x21C) /* DMA Channel 1 Command Register */ +#define FDADR2 (0x220) /* DMA Channel 2 Frame Descriptor Address Register */ +#define FDADR3 (0x230) /* DMA Channel 3 Frame Descriptor Address Register */ +#define FDADR4 (0x240) /* DMA Channel 4 Frame Descriptor Address Register */ +#define FDADR5 (0x250) /* DMA Channel 5 Frame Descriptor Address Register */ #define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */ -#define FSADR6 (0x264) /* DMA Channel 6 Frame Source Address Register */ -#define FIDR6 (0x268) /* DMA Channel 6 Frame ID Register */ #define LCCR0_ENB (1 << 0) /* LCD Controller enable */ #define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */ @@ -126,9 +125,6 @@ #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ #define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD))) -#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ -#define LCCR3_Bpp(Bpp) (((Bpp) << FShft (LCCR3_BPP))) - #define LCCR3_ACB Fld (8, 8) /* AC Bias */ #define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB))) @@ -157,8 +153,22 @@ #define LCSR_RD_ST (1 << 11) /* read status */ #define LCSR_CMD_INT (1 << 12) /* command interrupt */ +#define LCSR1_IU(x) (1 << ((x) + 23)) /* Input FIFO underrun */ +#define LCSR1_BS(x) (1 << ((x) + 15)) /* Branch Status */ +#define LCSR1_EOF(x) (1 << ((x) + 7)) /* End of Frame Status */ +#define LCSR1_SOF(x) (1 << ((x) - 1)) /* Start of Frame Status */ + #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ +/* overlay control registers */ +#define OVLxC1_PPL(x) ((((x) - 1) & 0x3ff) << 0) /* Pixels Per Line */ +#define OVLxC1_LPO(x) ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */ +#define OVLxC1_BPP(x) (((x) & 0xf) << 20) /* Bits Per Pixel */ +#define OVLxC1_OEN (1 << 31) /* Enable bit for Overlay */ +#define OVLxC2_XPOS(x) (((x) & 0x3ff) << 0) /* Horizontal Position */ +#define OVLxC2_YPOS(x) (((x) & 0x3ff) << 10) /* Vertical Position */ +#define OVL2C2_PFOR(x) (((x) & 0x7) << 20) /* Pixel Format */ + /* smartpanel related */ #define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */ #define PRSR_A0 (1 << 8) /* Read Data Source */ @@ -177,4 +187,11 @@ #define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff)) #define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff)) + +/* SMART_DELAY() is introduced for software controlled delay primitive which + * can be inserted between command sequences, unused command 0x6 is used here + * and delay ranges from 0ms ~ 255ms + */ +#define SMART_CMD_DELAY (0x6 << 9) +#define SMART_DELAY(ms) (SMART_CMD_DELAY | ((ms) & 0xff)) #endif /* __ASM_ARCH_REGS_LCD_H */ diff --git a/arch/arm/mach-pxa/include/mach/regs-uart.h b/arch/arm/mach-pxa/include/mach/regs-uart.h new file mode 100644 index 000000000000..55aeb7fb72f6 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-uart.h @@ -0,0 +1,143 @@ +#ifndef __ASM_ARCH_REGS_UART_H +#define __ASM_ARCH_REGS_UART_H + +/* + * UARTs + */ + +/* Full Function UART (FFUART) */ +#define FFUART FFRBR +#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ +#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ +#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ +#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ +#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ +#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ +#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ +#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ +#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ +#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ +#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ +#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Bluetooth UART (BTUART) */ +#define BTUART BTRBR +#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ +#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ +#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ +#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ +#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ +#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ +#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ +#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ +#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ +#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ +#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ +#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Standard UART (STUART) */ +#define STUART STRBR +#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ +#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ +#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ +#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ +#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ +#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ +#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ +#define STLSR __REG(0x40700014) /* Line Status Register (read only) */ +#define STMSR __REG(0x40700018) /* Reserved */ +#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ +#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ +#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Hardware UART (HWUART) */ +#define HWUART HWRBR +#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ +#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ +#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ +#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ +#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ +#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ +#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ +#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ +#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ +#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ +#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ +#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ +#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ +#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ +#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +#define IER_DMAE (1 << 7) /* DMA Requests Enable */ +#define IER_UUE (1 << 6) /* UART Unit Enable */ +#define IER_NRZE (1 << 5) /* NRZ coding Enable */ +#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ +#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ +#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ +#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ +#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ + +#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ +#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ +#define IIR_TOD (1 << 3) /* Time Out Detected */ +#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ +#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ +#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ + +#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ +#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ +#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ +#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ +#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ +#define FCR_ITL_1 (0) +#define FCR_ITL_8 (FCR_ITL1) +#define FCR_ITL_16 (FCR_ITL2) +#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) + +#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ +#define LCR_SB (1 << 6) /* Set Break */ +#define LCR_STKYP (1 << 5) /* Sticky Parity */ +#define LCR_EPS (1 << 4) /* Even Parity Select */ +#define LCR_PEN (1 << 3) /* Parity Enable */ +#define LCR_STB (1 << 2) /* Stop Bit */ +#define LCR_WLS1 (1 << 1) /* Word Length Select */ +#define LCR_WLS0 (1 << 0) /* Word Length Select */ + +#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ +#define LSR_TEMT (1 << 6) /* Transmitter Empty */ +#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ +#define LSR_BI (1 << 4) /* Break Interrupt */ +#define LSR_FE (1 << 3) /* Framing Error */ +#define LSR_PE (1 << 2) /* Parity Error */ +#define LSR_OE (1 << 1) /* Overrun Error */ +#define LSR_DR (1 << 0) /* Data Ready */ + +#define MCR_LOOP (1 << 4) +#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ +#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ +#define MCR_RTS (1 << 1) /* Request to Send */ +#define MCR_DTR (1 << 0) /* Data Terminal Ready */ + +#define MSR_DCD (1 << 7) /* Data Carrier Detect */ +#define MSR_RI (1 << 6) /* Ring Indicator */ +#define MSR_DSR (1 << 5) /* Data Set Ready */ +#define MSR_CTS (1 << 4) /* Clear To Send */ +#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ +#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ +#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ +#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ + +/* + * IrSR (Infrared Selection Register) + */ +#define STISR_RXPL (1 << 4) /* Receive Data Polarity */ +#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ +#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ +#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ +#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ + +#endif /* __ASM_ARCH_REGS_UART_H */ diff --git a/arch/arm/mach-pxa/include/mach/timex.h b/arch/arm/mach-pxa/include/mach/timex.h index b05fc6683c47..af6760a50e1a 100644 --- a/arch/arm/mach-pxa/include/mach/timex.h +++ b/arch/arm/mach-pxa/include/mach/timex.h @@ -10,6 +10,14 @@ * published by the Free Software Foundation. */ +/* Various drivers are still using the constant of CLOCK_TICK_RATE, for + * those drivers to at least work, the definition is provided here. + * + * NOTE: this is no longer accurate when multiple processors and boards + * are selected, newer drivers should not depend on this any more. Use + * either the clocksource/clockevent or get this at run-time by calling + * get_clock_tick_rate() (as defined in generic.c). + */ #if defined(CONFIG_PXA25x) /* PXA250/210 timer base */ diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h index 21e3e890af98..f4b029c03957 100644 --- a/arch/arm/mach-pxa/include/mach/uncompress.h +++ b/arch/arm/mach-pxa/include/mach/uncompress.h @@ -10,7 +10,7 @@ */ #include <linux/serial_reg.h> -#include <mach/pxa-regs.h> +#include <mach/regs-uart.h> #include <asm/mach-types.h> #define __REG(x) ((volatile unsigned long *)x) @@ -35,7 +35,7 @@ static inline void flush(void) static inline void arch_decomp_setup(void) { - if (machine_is_littleton()) + if (machine_is_littleton() || machine_is_intelmote2()) UART = STUART; } |
