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author | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2007-05-30 23:57:05 -0500 |
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committer | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2007-05-30 23:57:05 -0500 |
commit | 5bc65793cbf8da0d35f19ef025dda22887e79e80 (patch) | |
tree | 8291998abd73055de6f487fafa174ee2a5d3afee /arch/arm/mach-iop13xx/msi.c | |
parent | 6edae708bf77e012d855a7e2c7766f211d234f4f (diff) | |
parent | 3f0a6766e0cc5a577805732e5adb50a585c58175 (diff) | |
download | blackbird-op-linux-5bc65793cbf8da0d35f19ef025dda22887e79e80.tar.gz blackbird-op-linux-5bc65793cbf8da0d35f19ef025dda22887e79e80.zip |
[SCSI] Merge up to linux-2.6 head
Conflicts:
drivers/scsi/jazz_esp.c
Same changes made by both SCSI and SPARC trees: problem with UTF-8
conversion in the copyright.
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'arch/arm/mach-iop13xx/msi.c')
-rw-r--r-- | arch/arm/mach-iop13xx/msi.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c index 2d2369302220..63ef1124ca5c 100644 --- a/arch/arm/mach-iop13xx/msi.c +++ b/arch/arm/mach-iop13xx/msi.c @@ -30,52 +30,52 @@ static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS); /* IMIPR0 CP6 R8 Page 1 */ -static inline u32 read_imipr_0(void) +static u32 read_imipr_0(void) { u32 val; asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); return val; } -static inline void write_imipr_0(u32 val) +static void write_imipr_0(u32 val) { asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); } /* IMIPR1 CP6 R9 Page 1 */ -static inline u32 read_imipr_1(void) +static u32 read_imipr_1(void) { u32 val; asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); return val; } -static inline void write_imipr_1(u32 val) +static void write_imipr_1(u32 val) { asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); } /* IMIPR2 CP6 R10 Page 1 */ -static inline u32 read_imipr_2(void) +static u32 read_imipr_2(void) { u32 val; asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val)); return val; } -static inline void write_imipr_2(u32 val) +static void write_imipr_2(u32 val) { asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val)); } /* IMIPR3 CP6 R11 Page 1 */ -static inline u32 read_imipr_3(void) +static u32 read_imipr_3(void) { u32 val; asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val)); return val; } -static inline void write_imipr_3(u32 val) +static void write_imipr_3(u32 val) { asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val)); } @@ -190,5 +190,5 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) write_msi_msg(irq, &msg); set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); - return irq; + return 0; } |