summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/exynos4210-trats.dts
diff options
context:
space:
mode:
authorSylwester Nawrocki <s.nawrocki@samsung.com>2014-11-22 23:13:03 +0900
committerKukjin Kim <kgene.kim@samsung.com>2014-11-22 23:13:03 +0900
commit0357a4438d531ef3cf529e80ffcd208eb8e35f55 (patch)
treec18b74dcf9884572517c7ca186bcab103d33cf23 /arch/arm/boot/dts/exynos4210-trats.dts
parent432047f947bac093a4b322765fc2ce365353bc61 (diff)
downloadblackbird-op-linux-0357a4438d531ef3cf529e80ffcd208eb8e35f55.tar.gz
blackbird-op-linux-0357a4438d531ef3cf529e80ffcd208eb8e35f55.zip
ARM: dts: Specify default clocks for Exynos4 camera devices
Specify the default mux and divider clocks in device tree to ensure the FIMC devices on Trats, Trats2, Universal_c210 and Odroid X2/U3 boards are clocked from recommended clock source and with maximum supported frequency. For Trats2 also the MIPI-CSIS and the camera sensor clocks are configured, the 'clock-frequency' property is deprecated in favour of 'assigned-clock-rates' property. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/boot/dts/exynos4210-trats.dts')
-rw-r--r--arch/arm/boot/dts/exynos4210-trats.dts16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9e8b3a..720836205546 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -431,18 +431,34 @@
fimc_0: fimc@11800000 {
status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+ <&clock CLK_SCLK_FIMC0>;
+ assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <160000000>;
};
fimc_1: fimc@11810000 {
status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC1>,
+ <&clock CLK_SCLK_FIMC1>;
+ assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <160000000>;
};
fimc_2: fimc@11820000 {
status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC2>,
+ <&clock CLK_SCLK_FIMC2>;
+ assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <160000000>;
};
fimc_3: fimc@11830000 {
status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC3>,
+ <&clock CLK_SCLK_FIMC3>;
+ assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <160000000>;
};
};
};
OpenPOWER on IntegriCloud