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author | Arnd Bergmann <arnd@arndb.de> | 2014-05-23 23:02:49 +0200 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2014-05-23 23:02:49 +0200 |
commit | 77579afc35eeea20d3b34aad66dcbb6fdaf502da (patch) | |
tree | b640c86b4fee33493e5ea44633b8713c3e98c78c /arch/arm/boot/dts/at91sam9x5_isi.dtsi | |
parent | d5cd8605e2814d268cddee1ff1d95d9010b4e8eb (diff) | |
parent | b4a86b3810f5dc4b959ee69a3818c876752c88cd (diff) | |
download | blackbird-op-linux-77579afc35eeea20d3b34aad66dcbb6fdaf502da.tar.gz blackbird-op-linux-77579afc35eeea20d3b34aad66dcbb6fdaf502da.zip |
Merge tag 'at91-dt3' of git://github.com/at91linux/linux-at91 into next/dt
3.16 third DT series:
- move of both at91sam9n12 and at91sam9x5 to CCF
* tag 'at91-dt3' of git://github.com/at91linux/linux-at91:
ARM: at91: move sam9n12 SoC to the CCF
ARM: at91/dt: define sam9n12ek crystal frequencies
ARM: at91/dt: define sam9n12 clocks
ARM: at91: prepare common clk transition for sam9n12 SoC
ARM: at91: move sam9x5 SoCs to the CCF
ARM: at91/dt: define sam9x5ek's crystal frequencies
ARM: at91/dt: define sam9x5 clocks
ARM: at91: prepare common clk transition for sam9x5 SoCs
dt-bindings: clock: Move at91.h to dt-bindigs/clock
ARM: at91: fix spi cs on sama5d3 Xplained board
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/at91sam9x5_isi.dtsi')
-rw-r--r-- | arch/arm/boot/dts/at91sam9x5_isi.dtsi | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/at91sam9x5_isi.dtsi new file mode 100644 index 000000000000..98bc877a68ef --- /dev/null +++ b/arch/arm/boot/dts/at91sam9x5_isi.dtsi @@ -0,0 +1,26 @@ +/* + * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an + * Image Sensor Interface. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pmc: pmc@fffffc00 { + periphck { + isi_clk: isi_clk { + #clock-cells = <0>; + reg = <25>; + }; + }; + }; + }; + }; +}; |