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authorEnrico Weigelt, metux IT consult <info@metux.net>2019-03-11 14:57:59 +0100
committerVineet Gupta <vgupta@synopsys.com>2019-03-11 22:03:18 -0700
commit9a18b5a412baf23137c8fddb4ea7f0c14087f31c (patch)
tree5730aceeec989f7f08219c79231826de3906782d /arch/arc/plat-eznps
parent3032f0c9008088a3effdc2622ce16c3e1bcb13a2 (diff)
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arch: arc: Kconfig: pedantic formatting
Formatting of Kconfig files doesn't look so pretty, so let the Great White Handkerchief come around and clean it up. Signed-off-by: Enrico Weigelt, metux IT consult <info@metux.net> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/plat-eznps')
-rw-r--r--arch/arc/plat-eznps/Kconfig12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index 8eff057efcae..2eaecfb063a7 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -26,8 +26,8 @@ config EZNPS_MTM_EXT
help
Here we add new hierarchy for CPUs topology.
We got:
- Core
- Thread
+ Core
+ Thread
At the new thread level each CPU represent one HW thread.
At highest hierarchy each core contain 16 threads,
any of them seem like CPU from Linux point of view.
@@ -35,10 +35,10 @@ config EZNPS_MTM_EXT
core and HW scheduler round robin between them.
config EZNPS_MEM_ERROR_ALIGN
- bool "ARC-EZchip Memory error as an exception"
- depends on EZNPS_MTM_EXT
- default n
- help
+ bool "ARC-EZchip Memory error as an exception"
+ depends on EZNPS_MTM_EXT
+ default n
+ help
On the real chip of the NPS, user memory errors are handled
as a machine check exception, which is fatal, whereas on
simulator platform for NPS, is handled as a Level 2 interrupt
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