Merge tag 'arm-soc/for-4.5/devicetree' of http://github.com/Broadcom/stblinux into next/dt

Pull "Broadcom devicetree changes for v4.5¨ from Florian Fainelli:

This pull request contains the Broadcom ARM-based Device Tree changes for 4.5:

- Jon Mason enables the following for Broadcom Northstar Plus SoCs: PCI (using
  iProc PCI), NAND flash controller (BRCMNAND), TWD Timer and Watchdog
  (Cortex-A9), I2C (iProc), clock providers, does some Device Tree cleanups
  (re-parenting, fixing register sizes and hierarchy)

- Jon Mason also adds support for some reference Broadcom Northstar reference
  designs like the BCM5301X SVK reference boards, updates the existing binding
  documentation to cover the Northstar chips: 4708, 4709 and 53012.

- Pramod Kumar adds the GPIO to pinctrl mapping for the Broadcom Northstar Plus
  SoCs

- Yendapally Reddy Dhananjaya Reddy adds pinctrl Device Tree nodes for the
  Broadcom Northstar Plus SoCs device tree nodes

- Ray Jui adds Cygnus PCIe PHY Device Tree nodes and enables MSI for the iProc
  PCI controller on Cygnus platforms

- Kapil Hali adds SMP binding documentation and Device Tree nodes for the
  Northstar Plus SoCs

- Florian Fainelli adds clock provider support for the Broadcom BCM63138 DSL
  SoCs by utilizing the existing iProc ARM PLL controller, this includes a
  stable topic branch from Stephen Boyd to be merged

- Rafal Milecki adds missing LEDs for the Netgear R8000 router

* tag 'arm-soc/for-4.5/devicetree' of http://github.com/Broadcom/stblinux:
  ARM: dts: Enable MSI support for Broadcom Cygnus
  ARM: dts: Add SMP support for Broadcom NSP
  dt-bindings: add SMP enable-method for Broadcom NSP
  ARM: dts: enable pinctrl for Broadcom NSP
  ARM: dts: enable PCIe PHY support for Cygnus
  ARM: dts: Cygnus: define ngpios property in gpio controller's node
  ARM: BCM5301X: Add missing Netgear R8000 LEDs
  ARM: dts: BCM63xx: Add ARMPLL device tree nodes
  clk: bcm: Add BCM63138 clock support
  clk: iproc: Extend binding to cover BCM63138
  ARM: dts: enable clock support for Broadcom NSP
  ARM: dts: enable clock support for BCM5301X
  ARM: dts: NSP: Add I2C support to the DT
  ARM: dts: NSP: Device Tree clean-ups
  dts: pinctrl: Add GPIO to Pinctrl pin mapping in DT
  ARM: dts: bcm5301x: Add BCM SVK DT files
  dt-bindings: Add new SoCs to bcm4708 DT bindings
  ARM: dts: NSP: Add TWD Support to DT
  ARM: dts: NSP: Add NAND Support to DT
  ARM: dts: NSP: Add PCI support

4 files changed, 52 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt
index 6b0f49f6f499..8608a776caa7 100644
--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt
@@ -5,4 +5,11 @@ Boards with the BCM4708 SoC shall have the following properties:
 
 Required root node property:
 
+bcm4708
 compatible = "brcm,bcm4708";
+
+bcm4709
+compatible = "brcm,bcm4709";
+
+bcm53012
+compatible = "brcm,bcm53012";
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
new file mode 100644
index 000000000000..677ef9d9f445
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
@@ -0,0 +1,39 @@
+Broadcom Northstar Plus SoC CPU Enable Method
+---------------------------------------------
+This binding defines the enable method used for starting secondary
+CPU in the following Broadcom SoCs:
+  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
+
+The enable method is specified by defining the following required
+properties in the corresponding secondary "cpu" device tree node:
+  - enable-method = "brcm,bcm-nsp-smp";
+  - secondary-boot-reg = <...>;
+
+The secondary-boot-reg property is a u32 value that specifies the
+physical address of the register which should hold the common
+entry point for a secondary CPU. This entry is cpu node specific
+and should be added per cpu. E.g., in case of NSP (BCM58625) which
+is a dual core CPU SoC, this entry should be added to cpu1 node.
+
+
+Example:
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			enable-method = "brcm,bcm-nsp-smp";
+			secondary-boot-reg = <0xffff042c>;
+			reg = <1>;
+		};
+	};
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 3a07a87fef20..d1915549e009 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -190,6 +190,7 @@ nodes to be present and contain the properties described below.
 			    "allwinner,sun6i-a31"
 			    "allwinner,sun8i-a23"
 			    "arm,psci"
+			    "brcm,bcm-nsp-smp"
 			    "brcm,brahma-b15"
 			    "marvell,armada-375-smp"
 			    "marvell,armada-380-smp"
diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
index ede65a55e21b..0b35e71b39e8 100644
--- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
@@ -208,3 +208,8 @@ These clock IDs are defined in:
     ch3_unused	lcpll_ports	4	BCM_NS2_LCPLL_PORTS_CH3_UNUSED
     ch4_unused	lcpll_ports	5	BCM_NS2_LCPLL_PORTS_CH4_UNUSED
     ch5_unused	lcpll_ports	6	BCM_NS2_LCPLL_PORTS_CH5_UNUSED
+
+BCM63138
+--------
+PLL and leaf clock compatible strings for BCM63138 are:
+    "brcm,bcm63138-armpll"