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authorStephane Eranian <eranian@hpl.hp.com>2006-12-07 02:14:02 +0100
committerAndi Kleen <andi@basil.nowhere.org>2006-12-07 02:14:02 +0100
commit86efef50cfff9905c4e4ec64f3d3d3b299226674 (patch)
treee60029ca0b888b1f01a049d9e512ef524b2279e3 /Documentation/pcieaer-howto.txt
parentfa5cecd111d235819a1d807d43216ae459a0dd6f (diff)
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[PATCH] x86-64: x86-64 add Intel Core related PMU MSRs definitions
Add o the x86-64 tree a bunch of MSRs related to performance monitoring for the processors based on Intel Core microarchitecture. It also adds some architectural MSRs for PEBS. A similar patch for i386 will follow. changelog: - add Intel Precise-Event Based sampling (PEBS) related MSR - add Intel Data Save (DS) Area related MSR - add Intel Core microarchitecure performance counter MSRs Signed-off-by: stephane eranian <eranian@hpl.hp.com> Signed-off-by: Andi Kleen <ak@suse.de>
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