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authorGabriel Fernandez <gabriel.fernandez@linaro.org>2015-10-07 11:08:57 +0200
committerStephen Boyd <sboyd@codeaurora.org>2015-10-08 23:52:58 -0700
commit46a57afdd70c17cf15b2077c5ea611913f80f85f (patch)
treecbf4f7eb306e7a7bbb7f42b1c30820b48c5b6710 /Documentation/leds
parentfb4738629b6c06c24ba0649ece20ecec978d8694 (diff)
downloadblackbird-op-linux-46a57afdd70c17cf15b2077c5ea611913f80f85f.tar.gz
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drivers: clk: st: PLL rate change implementation for DVFS
Change A9 PLL rate, as per requirement from the cpufreq framework, for DVFS. For rate change, the A9 clock needs to be temporarily sourced from PLL external to A9 and then sourced back to A9-PLL Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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