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authorKieran Bingham <kieran+renesas@bingham.xyz>2016-06-30 13:50:30 -0300
committerMauro Carvalho Chehab <mchehab@s-opensource.com>2016-11-16 16:16:48 -0200
commit3547d32be04506ad23346eca6ce8b745ef146fab (patch)
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downloadblackbird-op-linux-3547d32be04506ad23346eca6ce8b745ef146fab.tar.gz
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[media] dt-bindings: Add Renesas R-Car FDP1 bindings
The FDP1 is a de-interlacing module which converts interlaced video to progressive video. It is also capable of performing pixel format conversion between YCbCr/YUV formats and RGB formats. Signed-off-by: Kieran Bingham <kieran+renesas@bingham.xyz> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
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+Renesas R-Car Fine Display Processor (FDP1)
+-------------------------------------------
+
+The FDP1 is a de-interlacing module which converts interlaced video to
+progressive video. It is capable of performing pixel format conversion between
+YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are supported as
+an input to the module.
+
+Required properties:
+
+ - compatible: must be "renesas,fdp1"
+ - reg: the register base and size for the device registers
+ - interrupts : interrupt specifier for the FDP1 instance
+ - clocks: reference to the functional clock
+
+Optional properties:
+
+ - power-domains: reference to the power domain that the FDP1 belongs to, if
+ any.
+ - renesas,fcp: a phandle referencing the FCP that handles memory accesses
+ for the FDP1. Not needed on Gen2, mandatory on Gen3.
+
+Please refer to the binding documentation for the clock and/or power domain
+providers for more details.
+
+
+Device node example
+-------------------
+
+ fdp1@fe940000 {
+ compatible = "renesas,fdp1";
+ reg = <0 0xfe940000 0 0x2400>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 119>;
+ power-domains = <&sysc R8A7795_PD_A3VP>;
+ renesas,fcp = <&fcpf0>;
+ };
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