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author | Frank Li <Frank.Li@freescale.com> | 2015-05-08 01:35:53 +0800 |
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committer | Shawn Guo <shawn.guo@linaro.org> | 2015-06-03 15:03:59 +0800 |
commit | ef69728f2fe52ec5786c28b1b4fa68689942ad19 (patch) | |
tree | a4a12061c20f28857b75aae50d239abc0617df6e /Documentation/devicetree/bindings/pinctrl | |
parent | 29eea64c1b8122f6c2f64401cd57bee042052dba (diff) | |
download | blackbird-op-linux-ef69728f2fe52ec5786c28b1b4fa68689942ad19.tar.gz blackbird-op-linux-ef69728f2fe52ec5786c28b1b4fa68689942ad19.zip |
Document: dt: binding: imx: update document for imx7d support
This part just add necessary change to boot imx7d.
Update clock, pinctrl and gpt for imx7d
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pinctrl')
-rw-r--r-- | Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt new file mode 100644 index 000000000000..8bbf25d58656 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt @@ -0,0 +1,27 @@ +* Freescale i.MX7 Dual IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part +and usage. + +Required properties: +- compatible: "fsl,imx7d-iomuxc" +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val + input_val> are specified using a PIN_FUNC_ID macro, which can be found in + imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual + Reference Manual for detailed CONFIG settings. + +CONFIG bits definition: +PAD_CTL_PUS_100K_DOWN (0 << 5) +PAD_CTL_PUS_5K_UP (1 << 5) +PAD_CTL_PUS_47K_UP (2 << 5) +PAD_CTL_PUS_100K_UP (3 << 5) +PAD_CTL_PUE (1 << 4) +PAD_CTL_HYS (1 << 3) +PAD_CTL_SRE_SLOW (1 << 2) +PAD_CTL_SRE_FAST (0 << 2) +PAD_CTL_DSE_X1 (0 << 0) +PAD_CTL_DSE_X2 (1 << 0) +PAD_CTL_DSE_X3 (2 << 0) +PAD_CTL_DSE_X4 (3 << 0) |