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| author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2013-08-09 22:27:14 +0200 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2013-09-30 14:58:17 +0000 |
| commit | 5b4deb6526bdea3b10b3717623aae171509e925f (patch) | |
| tree | c05c7388d700732911b671e0e0654cb72f840b69 /Documentation/devicetree/bindings/pci | |
| parent | 31f614edb726fcc4d5aa0f2895fbdec9b04a3ca4 (diff) | |
| download | blackbird-op-linux-5b4deb6526bdea3b10b3717623aae171509e925f.tar.gz blackbird-op-linux-5b4deb6526bdea3b10b3717623aae171509e925f.zip | |
PCI: mvebu: add support for MSI
This commit adds support for Message Signaled Interrupts in the
Marvell PCIe host controller. The work is very simple: it simply gets
a reference to the msi_chip associated to the PCIe controller thanks
to the msi-parent DT property, and stores this reference in the
pci_bus structure. This is enough to let the Linux PCI core use the
functions of msi_chip to setup and teardown MSIs.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Thierry Reding <thierry.reding@gmail.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/mvebu-pci.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt index 9556e2fedf6d..638673aec306 100644 --- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt @@ -14,6 +14,8 @@ Mandatory properties: - ranges: ranges describing the MMIO registers to control the PCIe interfaces, and ranges describing the MBus windows needed to access the memory and I/O regions of each PCIe interface. +- msi-parent: Link to the hardware entity that serves as the Message + Signaled Interrupt controller for this PCI controller. The ranges describing the MMIO registers have the following layout: @@ -86,6 +88,7 @@ pcie-controller { #size-cells = <2>; bus-range = <0x00 0xff>; + msi-parent = <&mpic>; ranges = <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ |
