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authorBrendan Higgins <brendanhiggins@google.com>2017-08-17 07:20:09 -0700
committerArnd Bergmann <arnd@arndb.de>2018-03-06 18:01:15 +0100
commitd6bdd009c21db3f677dd1d1bbb8c20bc819074bc (patch)
tree7bff38bb9bd9ef6995f7cb39ff4fb1949a7d338a /Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp
parent1796483fcdfbd657f10464bb988da57eaf6b37d3 (diff)
downloadblackbird-op-linux-d6bdd009c21db3f677dd1d1bbb8c20bc819074bc.tar.gz
blackbird-op-linux-d6bdd009c21db3f677dd1d1bbb8c20bc819074bc.zip
arm: dts: add Nuvoton NPCM750 device tree
Add a common device tree for all Nuvoton NPCM750 BMCs and a board specific device tree for the NPCM750 (Poleg) evaluation board. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Avi Fishman <avifishman70@gmail.com> Tested-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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+=========================================================
+Secondary CPU enable-method "nuvoton,npcm750-smp" binding
+=========================================================
+
+To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
+defined in the "cpus" node.
+
+Enable method name: "nuvoton,npcm750-smp"
+Compatible machines: "nuvoton,npcm750"
+Compatible CPUs: "arm,cortex-a9"
+Related properties: (none)
+
+Note:
+This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
+"nuvoton,npcm750-gcr".
+
+Example:
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "nuvoton,npcm750-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
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