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authorTomi Valkeinen <tomi.valkeinen@ti.com>2011-03-02 10:06:48 +0200
committerTomi Valkeinen <tomi.valkeinen@ti.com>2011-03-11 15:46:29 +0200
commitf2988ab9f4a2bf5e24f37d20eab1aad6862953d3 (patch)
tree2142e88f762550b667d2bc87915bad0584c897e0
parentbc6d4b1d3d9b7568fe88f5bb80d0266a7ef624cc (diff)
downloadblackbird-op-linux-f2988ab9f4a2bf5e24f37d20eab1aad6862953d3.tar.gz
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HACK: OMAP: DSS2: Fix OMAP2_DSS_USE_DSI_PLL
When using OMAP2_DSS_USE_DSI_PLL, which selects DSI PLL as source clock for DISPC, the DSI needs the vdds_dsi regulator. Latest regulator changes broke this, causing the the code to not acquire the regulator when using OMAP2_DSS_USE_DSI_PLL. This patch acquires the vdds_dsi regulator in dsi_pll_init(), fixing the issue. This is is just a quick hack to get the OMAP2_DSS_USE_DSI_PLL option working. There shouldn't be any other downside in this solution than some extra lines of code. OMAP2_DSS_USE_DSI_PLL is itself a big hack, and should be removed, and the feature itself should be implemented in a more sane way. However, the solution is not trivial, and people are using DSI PLL to get more exact pixel clocks, so this hack is an acceptable temporary solution for the time being. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
-rw-r--r--drivers/video/omap2/dss/dsi.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index 44b667b55ab8..be7694ff7ca7 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -1119,6 +1119,26 @@ int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
DSSDBG("PLL init\n");
+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
+ /*
+ * HACK: this is just a quick hack to get the USE_DSI_PLL
+ * option working. USE_DSI_PLL is itself a big hack, and
+ * should be removed.
+ */
+ if (dsi.vdds_dsi_reg == NULL) {
+ struct regulator *vdds_dsi;
+
+ vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi");
+
+ if (IS_ERR(vdds_dsi)) {
+ DSSERR("can't get VDDS_DSI regulator\n");
+ return PTR_ERR(vdds_dsi);
+ }
+
+ dsi.vdds_dsi_reg = vdds_dsi;
+ }
+#endif
+
enable_clocks(1);
dsi_enable_pll_clock(1);
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