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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2015-04-03 11:32:34 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2015-04-14 22:26:52 +0100 |
| commit | aaf4b5d92ce8299a363f1c0d7dc00aafde532e56 (patch) | |
| tree | a1cc24bf63db4e54e2fb3b528d6dd68a162a74dc | |
| parent | d3cd451dfb579367b4c5968256b3d8342dd0b0e8 (diff) | |
| download | blackbird-op-linux-aaf4b5d92ce8299a363f1c0d7dc00aafde532e56.tar.gz blackbird-op-linux-aaf4b5d92ce8299a363f1c0d7dc00aafde532e56.zip | |
ARM: cache-v7: optimise test for Cortex A9 r0pX devices
Eliminate one unnecessary instruction from this test by pre-shifting
the Cortex A9 ID - we can shift the actual ID in the teq instruction
thereby losing the pX bit of the ID at no cost.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 793d061b4dce..a134d8a13d00 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -97,10 +97,9 @@ ALT_UP( mov r3, r0, lsr #26) @ move LoUU into position #ifdef CONFIG_ARM_ERRATA_643719 ALT_SMP(mrc p15, 0, r2, c0, c0, 0) @ read main ID register ALT_UP( ret lr) @ LoUU is zero, so nothing to do - movw r1, #:lower16:0x410fc090 @ ID of ARM Cortex A9 r0p? - movt r1, #:upper16:0x410fc090 - bic r2, r2, #0x0000000f @ clear minor revision number - teq r2, r1 @ test for errata affected core and if so... + movw r1, #:lower16:(0x410fc090 >> 4) @ ID of ARM Cortex A9 r0p? + movt r1, #:upper16:(0x410fc090 >> 4) + teq r1, r2, lsr #4 @ test for errata affected core and if so... moveq r3, #1 << 1 @ fix LoUIS value beq start_flush_levels @ start flushing cache levels #endif |
