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authorJesse Barnes <jbarnes@virtuousgeek.org>2010-09-08 12:42:00 -0700
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-08 21:20:23 +0100
commit6176b8f908a58a7affaacf6f3a90ef14325686f0 (patch)
tree197fb78bf9b3a7f0500eb0ee0d3c06234e924d99
parent7eaf5547d0460027b15a297bb15d80bdd600cb41 (diff)
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drm/i915: use 125MHz reference clock for PCH attached eDP
Fix the test so we don't try to use the 450MHz refclk on PCH attached eDP. References: https://bugs.freedesktop.org/show_bug.cgi?id=29141 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 38bf7cd3d480..8c1da1efc063 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -246,8 +246,11 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
/* The clock divider is based off the hrawclk,
* and would like to run at 2MHz. So, take the
* hrawclk value and divide by 2 and use that
+ *
+ * Note that PCH attached eDP panels should use a 125MHz input
+ * clock divider.
*/
- if (IS_eDP(intel_dp)) {
+ if (IS_eDP(intel_dp) && !IS_PCH_eDP(intel_dp)) {
if (IS_GEN6(dev))
aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
else
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