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| author | Ben Skeggs <bskeggs@redhat.com> | 2015-01-14 15:28:47 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2015-01-22 12:18:02 +1000 |
| commit | 05c7145dae17a53b030238f477bf28211a21b736 (patch) | |
| tree | 11fdcf3012cf4e9b650e6312cbbeb20e8e9d45c4 | |
| parent | 5b85057acc411ee146ee4b230c773272ccee464d (diff) | |
| download | blackbird-op-linux-05c7145dae17a53b030238f477bf28211a21b736.tar.gz blackbird-op-linux-05c7145dae17a53b030238f477bf28211a21b736.zip | |
drm/nouveau/fifo: namespace + nvidia gpu names (no binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
22 files changed, 1126 insertions, 1188 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h index e81d40c221b5..9d6990aa5b47 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h @@ -248,5 +248,7 @@ #define nouveau_dmaeng nvkm_dmaeng #define nouveau_dmaobj nvkm_dmaobj #define nouveau_disp nvkm_disp +#define nouveau_fifo_chan nvkm_fifo_chan +#define nouveau_fifo nvkm_fifo #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h index 27f05de8fd0a..05321ce7ab15 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h @@ -1,15 +1,11 @@ -#ifndef __NOUVEAU_FIFO_H__ -#define __NOUVEAU_FIFO_H__ - +#ifndef __NVKM_FIFO_H__ +#define __NVKM_FIFO_H__ #include <core/namedb.h> -#include <core/gpuobj.h> -#include <core/engine.h> -#include <core/event.h> -struct nouveau_fifo_chan { - struct nouveau_namedb namedb; - struct nouveau_dmaobj *pushdma; - struct nouveau_gpuobj *pushgpu; +struct nvkm_fifo_chan { + struct nvkm_namedb namedb; + struct nvkm_dmaobj *pushdma; + struct nvkm_gpuobj *pushgpu; void __iomem *user; u64 addr; u32 size; @@ -17,110 +13,114 @@ struct nouveau_fifo_chan { atomic_t refcnt; /* NV04_NVSW_SET_REF */ }; -static inline struct nouveau_fifo_chan * -nouveau_fifo_chan(void *obj) +static inline struct nvkm_fifo_chan * +nvkm_fifo_chan(void *obj) { return (void *)nv_namedb(obj); } -#define nouveau_fifo_channel_create(p,e,c,b,a,s,n,m,d) \ - nouveau_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n), \ +#define nvkm_fifo_channel_create(p,e,c,b,a,s,n,m,d) \ + nvkm_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n), \ (m), sizeof(**d), (void **)d) -#define nouveau_fifo_channel_init(p) \ - nouveau_namedb_init(&(p)->namedb) -#define nouveau_fifo_channel_fini(p,s) \ - nouveau_namedb_fini(&(p)->namedb, (s)) - -int nouveau_fifo_channel_create_(struct nouveau_object *, - struct nouveau_object *, - struct nouveau_oclass *, +#define nvkm_fifo_channel_init(p) \ + nvkm_namedb_init(&(p)->namedb) +#define nvkm_fifo_channel_fini(p,s) \ + nvkm_namedb_fini(&(p)->namedb, (s)) + +int nvkm_fifo_channel_create_(struct nvkm_object *, + struct nvkm_object *, + struct nvkm_oclass *, int bar, u32 addr, u32 size, u32 push, u64 engmask, int len, void **); -void nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *); +void nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *); -#define _nouveau_fifo_channel_init _nouveau_namedb_init -#define _nouveau_fifo_channel_fini _nouveau_namedb_fini +#define _nvkm_fifo_channel_init _nvkm_namedb_init +#define _nvkm_fifo_channel_fini _nvkm_namedb_fini -void _nouveau_fifo_channel_dtor(struct nouveau_object *); -int _nouveau_fifo_channel_map(struct nouveau_object *, u64 *, u32 *); -u32 _nouveau_fifo_channel_rd32(struct nouveau_object *, u64); -void _nouveau_fifo_channel_wr32(struct nouveau_object *, u64, u32); -int _nouveau_fifo_channel_ntfy(struct nouveau_object *, u32, struct nvkm_event **); +void _nvkm_fifo_channel_dtor(struct nvkm_object *); +int _nvkm_fifo_channel_map(struct nvkm_object *, u64 *, u32 *); +u32 _nvkm_fifo_channel_rd32(struct nvkm_object *, u64); +void _nvkm_fifo_channel_wr32(struct nvkm_object *, u64, u32); +int _nvkm_fifo_channel_ntfy(struct nvkm_object *, u32, struct nvkm_event **); -struct nouveau_fifo_base { - struct nouveau_gpuobj gpuobj; +#include <core/gpuobj.h> + +struct nvkm_fifo_base { + struct nvkm_gpuobj gpuobj; }; -#define nouveau_fifo_context_create(p,e,c,g,s,a,f,d) \ - nouveau_gpuobj_create((p), (e), (c), 0, (g), (s), (a), (f), (d)) -#define nouveau_fifo_context_destroy(p) \ - nouveau_gpuobj_destroy(&(p)->gpuobj) -#define nouveau_fifo_context_init(p) \ - nouveau_gpuobj_init(&(p)->gpuobj) -#define nouveau_fifo_context_fini(p,s) \ - nouveau_gpuobj_fini(&(p)->gpuobj, (s)) +#define nvkm_fifo_context_create(p,e,c,g,s,a,f,d) \ + nvkm_gpuobj_create((p), (e), (c), 0, (g), (s), (a), (f), (d)) +#define nvkm_fifo_context_destroy(p) \ + nvkm_gpuobj_destroy(&(p)->gpuobj) +#define nvkm_fifo_context_init(p) \ + nvkm_gpuobj_init(&(p)->gpuobj) +#define nvkm_fifo_context_fini(p,s) \ + nvkm_gpuobj_fini(&(p)->gpuobj, (s)) + +#define _nvkm_fifo_context_dtor _nvkm_gpuobj_dtor +#define _nvkm_fifo_context_init _nvkm_gpuobj_init +#define _nvkm_fifo_context_fini _nvkm_gpuobj_fini +#define _nvkm_fifo_context_rd32 _nvkm_gpuobj_rd32 +#define _nvkm_fifo_context_wr32 _nvkm_gpuobj_wr32 -#define _nouveau_fifo_context_dtor _nouveau_gpuobj_dtor -#define _nouveau_fifo_context_init _nouveau_gpuobj_init -#define _nouveau_fifo_context_fini _nouveau_gpuobj_fini -#define _nouveau_fifo_context_rd32 _nouveau_gpuobj_rd32 -#define _nouveau_fifo_context_wr32 _nouveau_gpuobj_wr32 +#include <core/engine.h> +#include <core/event.h> -struct nouveau_fifo { - struct nouveau_engine base; +struct nvkm_fifo { + struct nvkm_engine base; struct nvkm_event cevent; /* channel creation event */ struct nvkm_event uevent; /* async user trigger */ - struct nouveau_object **channel; + struct nvkm_object **channel; spinlock_t lock; u16 min; u16 max; - int (*chid)(struct nouveau_fifo *, struct nouveau_object *); - void (*pause)(struct nouveau_fifo *, unsigned long *); - void (*start)(struct nouveau_fifo *, unsigned long *); + int (*chid)(struct nvkm_fifo *, struct nvkm_object *); + void (*pause)(struct nvkm_fifo *, unsigned long *); + void (*start)(struct nvkm_fifo *, unsigned long *); }; -static inline struct nouveau_fifo * -nouveau_fifo(void *obj) +static inline struct nvkm_fifo * +nvkm_fifo(void *obj) { - return (void *)nouveau_engine(obj, NVDEV_ENGINE_FIFO); + return (void *)nvkm_engine(obj, NVDEV_ENGINE_FIFO); } -#define nouveau_fifo_create(o,e,c,fc,lc,d) \ - nouveau_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d) -#define nouveau_fifo_init(p) \ - nouveau_engine_init(&(p)->base) -#define nouveau_fifo_fini(p,s) \ - nouveau_engine_fini(&(p)->base, (s)) +#define nvkm_fifo_create(o,e,c,fc,lc,d) \ + nvkm_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d) +#define nvkm_fifo_init(p) \ + nvkm_engine_init(&(p)->base) +#define nvkm_fifo_fini(p,s) \ + nvkm_engine_fini(&(p)->base, (s)) -int nouveau_fifo_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int min, int max, +int nvkm_fifo_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int min, int max, int size, void **); -void nouveau_fifo_destroy(struct nouveau_fifo *); +void nvkm_fifo_destroy(struct nvkm_fifo *); const char * -nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid); - -#define _nouveau_fifo_init _nouveau_engine_init -#define _nouveau_fifo_fini _nouveau_engine_fini - -extern struct nouveau_oclass *nv04_fifo_oclass; -extern struct nouveau_oclass *nv10_fifo_oclass; -extern struct nouveau_oclass *nv17_fifo_oclass; -extern struct nouveau_oclass *nv40_fifo_oclass; -extern struct nouveau_oclass *nv50_fifo_oclass; -extern struct nouveau_oclass *nv84_fifo_oclass; -extern struct nouveau_oclass *nvc0_fifo_oclass; -extern struct nouveau_oclass *nve0_fifo_oclass; -extern struct nouveau_oclass *gk20a_fifo_oclass; -extern struct nouveau_oclass *nv108_fifo_oclass; - -int nouveau_fifo_uevent_ctor(struct nouveau_object *, void *, u32, - struct nvkm_notify *); -void nouveau_fifo_uevent(struct nouveau_fifo *); - -void nv04_fifo_intr(struct nouveau_subdev *); -int nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *); - +nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid); + +#define _nvkm_fifo_init _nvkm_engine_init +#define _nvkm_fifo_fini _nvkm_engine_fini + +extern struct nvkm_oclass *nv04_fifo_oclass; +extern struct nvkm_oclass *nv10_fifo_oclass; +extern struct nvkm_oclass *nv17_fifo_oclass; +extern struct nvkm_oclass *nv40_fifo_oclass; +extern struct nvkm_oclass *nv50_fifo_oclass; +extern struct nvkm_oclass *g84_fifo_oclass; +extern struct nvkm_oclass *gf100_fifo_oclass; +extern struct nvkm_oclass *gk104_fifo_oclass; +extern struct nvkm_oclass *gk20a_fifo_oclass; +extern struct nvkm_oclass *gk208_fifo_oclass; + +int nvkm_fifo_uevent_ctor(struct nvkm_object *, void *, u32, + struct nvkm_notify *); +void nvkm_fifo_uevent(struct nvkm_fifo *); + +void nv04_fifo_intr(struct nvkm_subdev *); +int nv04_fifo_context_attach(struct nvkm_object *, struct nvkm_object *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 1d851d61f982..bcdc5bdd10cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -84,7 +84,7 @@ gm100_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; #endif device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass; @@ -128,7 +128,7 @@ gm100_identify(struct nouveau_device *device) #endif device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; #if 0 - device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index e4baae226379..f48fd5a22f26 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -106,7 +106,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; @@ -135,7 +135,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; @@ -164,7 +164,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; @@ -193,7 +193,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; @@ -222,7 +222,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; @@ -251,7 +251,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass; @@ -280,7 +280,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; @@ -309,7 +309,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass; @@ -338,7 +338,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass; @@ -368,7 +368,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; @@ -399,7 +399,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass; @@ -429,7 +429,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass; @@ -459,7 +459,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c index 9a4e062656ac..3ebf7172835b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c @@ -81,7 +81,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; @@ -114,7 +114,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; @@ -147,7 +147,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; @@ -179,7 +179,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; @@ -212,7 +212,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; @@ -244,7 +244,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; @@ -276,7 +276,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; @@ -309,7 +309,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; @@ -339,7 +339,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c index 91aea039bfb1..cc06a67bbeac 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c @@ -81,7 +81,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass; @@ -115,7 +115,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass; @@ -149,7 +149,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass; @@ -205,7 +205,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; @@ -239,7 +239,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; @@ -273,7 +273,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; @@ -306,7 +306,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild index f38820faf44f..c5a2d8718c5b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild @@ -4,8 +4,8 @@ nvkm-y += nvkm/engine/fifo/nv10.o nvkm-y += nvkm/engine/fifo/nv17.o nvkm-y += nvkm/engine/fifo/nv40.o nvkm-y += nvkm/engine/fifo/nv50.o -nvkm-y += nvkm/engine/fifo/nv84.o -nvkm-y += nvkm/engine/fifo/nvc0.o -nvkm-y += nvkm/engine/fifo/nve0.o +nvkm-y += nvkm/engine/fifo/g84.o +nvkm-y += nvkm/engine/fifo/gf100.o +nvkm-y += nvkm/engine/fifo/gk104.o nvkm-y += nvkm/engine/fifo/gk20a.o -nvkm-y += nvkm/engine/fifo/nv108.o +nvkm-y += nvkm/engine/fifo/gk208.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c index 7e54a521bc05..fa223f88d25e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c @@ -21,23 +21,21 @@ * * Authors: Ben Skeggs */ +#include <engine/fifo.h> #include <core/client.h> #include <core/device.h> -#include <core/notify.h> -#include <core/object.h> #include <core/handle.h> -#include <core/event.h> -#include <nvif/unpack.h> +#include <core/notify.h> +#include <engine/dmaobj.h> + #include <nvif/class.h> #include <nvif/event.h> - -#include <engine/dmaobj.h> -#include <engine/fifo.h> +#include <nvif/unpack.h> static int -nouveau_fifo_event_ctor(struct nouveau_object *object, void *data, u32 size, - struct nvkm_notify *notify) +nvkm_fifo_event_ctor(struct nvkm_object *object, void *data, u32 size, + struct nvkm_notify *notify) { if (size == 0) { notify->size = 0; @@ -49,33 +47,33 @@ nouveau_fifo_event_ctor(struct nouveau_object *object, void *data, u32 size, } static const struct nvkm_event_func -nouveau_fifo_event_func = { - .ctor = nouveau_fifo_event_ctor, +nvkm_fifo_event_func = { + .ctor = nvkm_fifo_event_ctor, }; int -nouveau_fifo_channel_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, - int bar, u32 addr, u32 size, u32 pushbuf, - u64 engmask, int len, void **ptr) +nvkm_fifo_channel_create_(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, + int bar, u32 addr, u32 size, u32 pushbuf, + u64 engmask, int len, void **ptr) { - struct nouveau_device *device = nv_device(engine); - struct nouveau_fifo *priv = (void *)engine; - struct nouveau_fifo_chan *chan; - struct nouveau_dmaeng *dmaeng; + struct nvkm_device *device = nv_device(engine); + struct nvkm_fifo *priv = (void *)engine; + struct nvkm_fifo_chan *chan; + struct nvkm_dmaeng *dmaeng; unsigned long flags; int ret; /* create base object class */ - ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL, - engmask, len, ptr); + ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL, + engmask, len, ptr); chan = *ptr; if (ret) return ret; /* validate dma object representing push buffer */ - chan->pushdma = (void *)nouveau_handle_ref(parent, pushbuf); + chan->pushdma = (void *)nvkm_handle_ref(parent, pushbuf); if (!chan->pushdma) return -ENOENT; @@ -115,9 +113,9 @@ nouveau_fifo_channel_create_(struct nouveau_object *parent, } void -nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *chan) +nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *chan) { - struct nouveau_fifo *priv = (void *)nv_object(chan)->engine; + struct nvkm_fifo *priv = (void *)nv_object(chan)->engine; unsigned long flags; if (chan->user) @@ -127,31 +125,31 @@ nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *chan) priv->channel[chan->chid] = NULL; spin_unlock_irqrestore(&priv->lock, flags); - nouveau_gpuobj_ref(NULL, &chan->pushgpu); - nouveau_object_ref(NULL, (struct nouveau_object **)&chan->pushdma); - nouveau_namedb_destroy(&chan->namedb); + nvkm_gpuobj_ref(NULL, &chan->pushgpu); + nvkm_object_ref(NULL, (struct nvkm_object **)&chan->pushdma); + nvkm_namedb_destroy(&chan->namedb); } void -_nouveau_fifo_channel_dtor(struct nouveau_object *object) +_nvkm_fifo_channel_dtor(struct nvkm_object *object) { - struct nouveau_fifo_chan *chan = (void *)object; - nouveau_fifo_channel_destroy(chan); + struct nvkm_fifo_chan *chan = (void *)object; + nvkm_fifo_channel_destroy(chan); } int -_nouveau_fifo_channel_map(struct nouveau_object *object, u64 *addr, u32 *size) +_nvkm_fifo_channel_map(struct nvkm_object *object, u64 *addr, u32 *size) { - struct nouveau_fifo_chan *chan = (void *)object; + struct nvkm_fifo_chan *chan = (void *)object; *addr = chan->addr; *size = chan->size; return 0; } u32 -_nouveau_fifo_channel_rd32(struct nouveau_object *object, u64 addr) +_nvkm_fifo_channel_rd32(struct nvkm_object *object, u64 addr) { - struct nouveau_fifo_chan *chan = (void *)object; + struct nvkm_fifo_chan *chan = (void *)object; if (unlikely(!chan->user)) { chan->user = ioremap(chan->addr, chan->size); if (WARN_ON_ONCE(chan->user == NULL)) @@ -161,9 +159,9 @@ _nouveau_fifo_channel_rd32(struct nouveau_object *object, u64 addr) } void -_nouveau_fifo_channel_wr32(struct nouveau_object *object, u64 addr, u32 data) +_nvkm_fifo_channel_wr32(struct nvkm_object *object, u64 addr, u32 data) { - struct nouveau_fifo_chan *chan = (void *)object; + struct nvkm_fifo_chan *chan = (void *)object; if (unlikely(!chan->user)) { chan->user = ioremap(chan->addr, chan->size); if (WARN_ON_ONCE(chan->user == NULL)) @@ -173,8 +171,8 @@ _nouveau_fifo_channel_wr32(struct nouveau_object *object, u64 addr, u32 data) } int -nouveau_fifo_uevent_ctor(struct nouveau_object *object, void *data, u32 size, - struct nvkm_notify *notify) +nvkm_fifo_uevent_ctor(struct nvkm_object *object, void *data, u32 size, + struct nvkm_notify *notify) { union { struct nvif_notify_uevent_req none; @@ -191,7 +189,7 @@ nouveau_fifo_uevent_ctor(struct nouveau_object *object, void *data, u32 size, } void -nouveau_fifo_uevent(struct nouveau_fifo *fifo) +nvkm_fifo_uevent(struct nvkm_fifo *fifo) { struct nvif_notify_uevent_rep rep = { }; @@ -199,10 +197,10 @@ nouveau_fifo_uevent(struct nouveau_fifo *fifo) } int -_nouveau_fifo_channel_ntfy(struct nouveau_object *object, u32 type, - struct nvkm_event **event) +_nvkm_fifo_channel_ntfy(struct nvkm_object *object, u32 type, + struct nvkm_event **event) { - struct nouveau_fifo *fifo = (void *)object->engine; + struct nvkm_fifo *fifo = (void *)object->engine; switch (type) { case G82_CHANNEL_DMA_V0_NTFY_UEVENT: if (nv_mclass(object) >= G82_CHANNEL_DMA) { @@ -217,14 +215,14 @@ _nouveau_fifo_channel_ntfy(struct nouveau_object *object, u32 type, } static int -nouveau_fifo_chid(struct nouveau_fifo *priv, struct nouveau_object *object) +nvkm_fifo_chid(struct nvkm_fifo *priv, struct nvkm_object *object) { int engidx = nv_hclass(priv) & 0xff; while (object && object->parent) { if ( nv_iclass(object->parent, NV_ENGCTX_CLASS) && (nv_hclass(object->parent) & 0xff) == engidx) - return nouveau_fifo_chan(object)->chid; + return nvkm_fifo_chan(object)->chid; object = object->parent; } @@ -232,9 +230,9 @@ nouveau_fifo_chid(struct nouveau_fifo *priv, struct nouveau_object *object) } const char * -nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid) +nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid) { - struct nouveau_fifo_chan *chan = NULL; + struct nvkm_fifo_chan *chan = NULL; unsigned long flags; spin_lock_irqsave(&fifo->lock, flags); @@ -242,29 +240,28 @@ nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid) chan = (void *)fifo->channel[chid]; spin_unlock_irqrestore(&fifo->lock, flags); - return nouveau_client_name(chan); + return nvkm_client_name(chan); } void -nouveau_fifo_destroy(struct nouveau_fifo *priv) +nvkm_fifo_destroy(struct nvkm_fifo *priv) { kfree(priv->channel); nvkm_event_fini(&priv->uevent); nvkm_event_fini(&priv->cevent); - nouveau_engine_destroy(&priv->base); + nvkm_engine_destroy(&priv->base); } int -nouveau_fifo_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, - int min, int max, int length, void **pobject) +nvkm_fifo_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, + int min, int max, int length, void **pobject) { - struct nouveau_fifo *priv; + struct nvkm_fifo *priv; int ret; - ret = nouveau_engine_create_(parent, engine, oclass, true, "PFIFO", - "fifo", length, pobject); + ret = nvkm_engine_create_(parent, engine, oclass, true, "PFIFO", + "fifo", length, pobject); priv = *pobject; if (ret) return ret; @@ -275,11 +272,11 @@ nouveau_fifo_create_(struct nouveau_object *parent, if (!priv->channel) return -ENOMEM; - ret = nvkm_event_init(&nouveau_fifo_event_func, 1, 1, &priv->cevent); + ret = nvkm_event_init(&nvkm_fifo_event_func, 1, 1, &priv->cevent); if (ret) return ret; - priv->chid = nouveau_fifo_chid; + priv->chid = nvkm_fifo_chid; spin_lock_init(&priv->lock); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c index 727358d8ac77..a04920b3cf84 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c @@ -21,35 +21,29 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" +#include "nv04.h" -#include <core/os.h> #include <core/client.h> #include <core/engctx.h> #include <core/ramht.h> -#include <core/event.h> -#include <nvif/unpack.h> -#include <nvif/class.h> - -#include <subdev/timer.h> #include <subdev/bar.h> +#include <subdev/mmu.h> +#include <subdev/timer.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> - -#include "nv04.h" -#include "nv50.h" +#include <nvif/class.h> +#include <nvif/unpack.h> /******************************************************************************* * FIFO channel objects ******************************************************************************/ static int -nv84_fifo_context_attach(struct nouveau_object *parent, - struct nouveau_object *object) +g84_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent->parent; - struct nouveau_gpuobj *ectx = (void *)object; + struct nvkm_gpuobj *ectx = (void *)object; u64 limit = ectx->addr + ectx->size - 1; u64 start = ectx->addr; u32 addr; @@ -83,10 +77,10 @@ nv84_fifo_context_attach(struct nouveau_object *parent, } static int -nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend, - struct nouveau_object *object) +g84_fifo_context_detach(struct nvkm_object *parent, bool suspend, + struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_priv *priv = (void *)parent->engine; struct nv50_fifo_base *base = (void *)parent->parent; struct nv50_fifo_chan *chan = (void *)parent; @@ -115,7 +109,7 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend, nv_wr32(priv, 0x002520, save); if (!done) { nv_error(priv, "channel %d [%s] unload timeout\n", - chan->base.chid, nouveau_client_name(chan)); + chan->base.chid, nvkm_client_name(chan)); if (suspend) return -EBUSY; } @@ -131,8 +125,8 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend, } static int -nv84_fifo_object_attach(struct nouveau_object *parent, - struct nouveau_object *object, u32 handle) +g84_fifo_object_attach(struct nvkm_object *parent, + struct nvkm_object *object, u32 handle) { struct nv50_fifo_chan *chan = (void *)parent; u32 context; @@ -161,19 +155,18 @@ nv84_fifo_object_attach(struct nouveau_object *parent, return -EINVAL; } - return nouveau_ramht_insert(chan->ramht, 0, handle, context); + return nvkm_ramht_insert(chan->ramht, 0, handle, context); } static int -nv84_fifo_chan_ctor_dma(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv03_channel_dma_v0 v0; } *args = data; - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent; struct nv50_fifo_chan *chan; int ret; @@ -186,36 +179,36 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x2000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG) | - (1ULL << NVDEV_ENGINE_ME) | - (1ULL << NVDEV_ENGINE_VP) | - (1ULL << NVDEV_ENGINE_CIPHER) | - (1ULL << NVDEV_ENGINE_SEC) | - (1ULL << NVDEV_ENGINE_BSP) | - (1ULL << NVDEV_ENGINE_MSVLD) | - (1ULL << NVDEV_ENGINE_MSPDEC) | - (1ULL << NVDEV_ENGINE_MSPPP) | - (1ULL << NVDEV_ENGINE_CE0) | - (1ULL << NVDEV_ENGINE_VIC), &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, + 0x2000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG) | + (1ULL << NVDEV_ENGINE_ME) | + (1ULL << NVDEV_ENGINE_VP) | + (1ULL << NVDEV_ENGINE_CIPHER) | + (1ULL << NVDEV_ENGINE_SEC) | + (1ULL << NVDEV_ENGINE_BSP) | + (1ULL << NVDEV_ENGINE_MSVLD) | + (1ULL << NVDEV_ENGINE_MSPDEC) | + (1ULL << NVDEV_ENGINE_MSPPP) | + (1ULL << NVDEV_ENGINE_CE0) | + (1ULL << NVDEV_ENGINE_VIC), &chan); *pobject = nv_object(chan); if (ret) return ret; args->v0.chid = chan->base.chid; - ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, - &chan->ramht); + ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, + &chan->ramht); if (ret) return ret; - nv_parent(chan)->context_attach = nv84_fifo_context_attach; - nv_parent(chan)->context_detach = nv84_fifo_context_detach; - nv_parent(chan)->object_attach = nv84_fifo_object_attach; + nv_parent(chan)->context_attach = g84_fifo_context_attach; + nv_parent(chan)->context_detach = g84_fifo_context_detach; + nv_parent(chan)->object_attach = g84_fifo_object_attach; nv_parent(chan)->object_detach = nv50_fifo_object_detach; nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); @@ -239,15 +232,14 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent, } static int -nv84_fifo_chan_ctor_ind(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv50_channel_gpfifo_v0 v0; } *args = data; - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent; struct nv50_fifo_chan *chan; u64 ioffset, ilength; @@ -262,36 +254,36 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x2000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG) | - (1ULL << NVDEV_ENGINE_ME) | - (1ULL << NVDEV_ENGINE_VP) | - (1ULL << NVDEV_ENGINE_CIPHER) | - (1ULL << NVDEV_ENGINE_SEC) | - (1ULL << NVDEV_ENGINE_BSP) | - (1ULL << NVDEV_ENGINE_MSVLD) | - (1ULL << NVDEV_ENGINE_MSPDEC) | - (1ULL << NVDEV_ENGINE_MSPPP) | - (1ULL << NVDEV_ENGINE_CE0) | - (1ULL << NVDEV_ENGINE_VIC), &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, + 0x2000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG) | + (1ULL << NVDEV_ENGINE_ME) | + (1ULL << NVDEV_ENGINE_VP) | + (1ULL << NVDEV_ENGINE_CIPHER) | + (1ULL << NVDEV_ENGINE_SEC) | + (1ULL << NVDEV_ENGINE_BSP) | + (1ULL << NVDEV_ENGINE_MSVLD) | + (1ULL << NVDEV_ENGINE_MSPDEC) | + (1ULL << NVDEV_ENGINE_MSPPP) | + (1ULL << NVDEV_ENGINE_CE0) | + (1ULL << NVDEV_ENGINE_VIC), &chan); *pobject = nv_object(chan); if (ret) return ret; args->v0.chid = chan->base.chid; - ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, - &chan->ramht); + ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, + &chan->ramht); if (ret) return ret; - nv_parent(chan)->context_attach = nv84_fifo_context_attach; - nv_parent(chan)->context_detach = nv84_fifo_context_detach; - nv_parent(chan)->object_attach = nv84_fifo_object_attach; + nv_parent(chan)->context_attach = g84_fifo_context_attach; + nv_parent(chan)->context_detach = g84_fifo_context_detach; + nv_parent(chan)->object_attach = g84_fifo_object_attach; nv_parent(chan)->object_detach = nv50_fifo_object_detach; ioffset = args->v0.ioffset; @@ -315,16 +307,16 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent, } static int -nv84_fifo_chan_init(struct nouveau_object *object) +g84_fifo_chan_init(struct nvkm_object *object) { struct nv50_fifo_priv *priv = (void *)object->engine; struct nv50_fifo_base *base = (void *)object->parent; struct nv50_fifo_chan *chan = (void *)object; - struct nouveau_gpuobj *ramfc = base->ramfc; + struct nvkm_gpuobj *ramfc = base->ramfc; u32 chid = chan->base.chid; int ret; - ret = nouveau_fifo_channel_init(&chan->base); + ret = nvkm_fifo_channel_init(&chan->base); if (ret) return ret; @@ -333,34 +325,34 @@ nv84_fifo_chan_init(struct nouveau_object *object) return 0; } -static struct nouveau_ofuncs -nv84_fifo_ofuncs_dma = { - .ctor = nv84_fifo_chan_ctor_dma, +static struct nvkm_ofuncs +g84_fifo_ofuncs_dma = { + .ctor = g84_fifo_chan_ctor_dma, .dtor = nv50_fifo_chan_dtor, - .init = nv84_fifo_chan_init, + .init = g84_fifo_chan_init, .fini = nv50_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_ofuncs -nv84_fifo_ofuncs_ind = { - .ctor = nv84_fifo_chan_ctor_ind, +static struct nvkm_ofuncs +g84_fifo_ofuncs_ind = { + .ctor = g84_fifo_chan_ctor_ind, .dtor = nv50_fifo_chan_dtor, - .init = nv84_fifo_chan_init, + .init = g84_fifo_chan_init, .fini = nv50_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_oclass -nv84_fifo_sclass[] = { - { G82_CHANNEL_DMA, &nv84_fifo_ofuncs_dma }, - { G82_CHANNEL_GPFIFO, &nv84_fifo_ofuncs_ind }, +static struct nvkm_oclass +g84_fifo_sclass[] = { + { G82_CHANNEL_DMA, &g84_fifo_ofuncs_dma }, + { G82_CHANNEL_GPFIFO, &g84_fifo_ofuncs_ind }, {} }; @@ -369,57 +361,56 @@ nv84_fifo_sclass[] = { ******************************************************************************/ static int -nv84_fifo_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g84_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_fifo_base *base; int ret; - ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000, - 0x1000, NVOBJ_FLAG_HEAP, &base); + ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000, + 0x1000, NVOBJ_FLAG_HEAP, &base); *pobject = nv_object(base); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0, - NVOBJ_FLAG_ZERO_ALLOC, &base->eng); + ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0, + NVOBJ_FLAG_ZERO_ALLOC, &base->eng); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, - 0, &base->pgd); + ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, + 0, &base->pgd); if (ret) return ret; - ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd); + ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1000, - 0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache); + ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x1000, + 0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0100, - 0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc); + ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0100, + 0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc); if (ret) return ret; return 0; } -static struct nouveau_oclass -nv84_fifo_cclass = { +static struct nvkm_oclass +g84_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0x84), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv84_fifo_context_ctor, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g84_fifo_context_ctor, .dtor = nv50_fifo_context_dtor, - .init = _nouveau_fifo_context_init, - .fini = _nouveau_fifo_context_fini, - .rd32 = _nouveau_fifo_context_rd32, - .wr32 = _nouveau_fifo_context_wr32, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, }, }; @@ -428,69 +419,69 @@ nv84_fifo_cclass = { ******************************************************************************/ static void -nv84_fifo_uevent_init(struct nvkm_event *event, int type, int index) +g84_fifo_uevent_init(struct nvkm_event *event, int type, int index) { - struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); nv_mask(fifo, 0x002140, 0x40000000, 0x40000000); } static void -nv84_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +g84_fifo_uevent_fini(struct nvkm_event *event, int type, int index) { - struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); nv_mask(fifo, 0x002140, 0x40000000, 0x00000000); } static const struct nvkm_event_func -nv84_fifo_uevent_func = { - .ctor = nouveau_fifo_uevent_ctor, - .init = nv84_fifo_uevent_init, - .fini = nv84_fifo_uevent_fini, +g84_fifo_uevent_func = { + .ctor = nvkm_fifo_uevent_ctor, + .init = g84_fifo_uevent_init, + .fini = g84_fifo_uevent_fini, }; static int -nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g84_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_fifo_priv *priv; int ret; - ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv); + ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, - &priv->playlist[0]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, + &priv->playlist[0]); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, - &priv->playlist[1]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, + &priv->playlist[1]); if (ret) return ret; - ret = nvkm_event_init(&nv84_fifo_uevent_func, 1, 1, &priv->base.uevent); + ret = nvkm_event_init(&g84_fifo_uevent_func, 1, 1, &priv->base.uevent); if (ret) return ret; nv_subdev(priv)->unit = 0x00000100; nv_subdev(priv)->intr = nv04_fifo_intr; - nv_engine(priv)->cclass = &nv84_fifo_cclass; - nv_engine(priv)->sclass = nv84_fifo_sclass; + nv_engine(priv)->cclass = &g84_fifo_cclass; + nv_engine(priv)->sclass = g84_fifo_sclass; priv->base.pause = nv04_fifo_pause; priv->base.start = nv04_fifo_start; return 0; } -struct nouveau_oclass * -nv84_fifo_oclass = &(struct nouveau_oclass) { +struct nvkm_oclass * +g84_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0x84), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv84_fifo_ctor, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g84_fifo_ctor, .dtor = nv50_fifo_dtor, .init = nv50_fifo_init, - .fini = _nouveau_fifo_fini, + .fini = _nvkm_fifo_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c index 6e05b0b706fa..b745252f2261 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -21,52 +21,47 @@ * * Authors: Ben Skeggs */ +#include <engine/fifo.h> #include <core/client.h> -#include <core/handle.h> -#include <core/namedb.h> -#include <core/gpuobj.h> #include <core/engctx.h> -#include <core/event.h> -#include <nvif/unpack.h> -#include <nvif/class.h> #include <core/enum.h> - -#include <subdev/timer.h> +#include <core/handle.h> #include <subdev/bar.h> #include <subdev/fb.h> #include <subdev/mmu.h> +#include <subdev/timer.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> +#include <nvif/class.h> +#include <nvif/unpack.h> -struct nvc0_fifo_priv { - struct nouveau_fifo base; +struct gf100_fifo_priv { + struct nvkm_fifo base; struct work_struct fault; u64 mask; struct { - struct nouveau_gpuobj *mem[2]; + struct nvkm_gpuobj *mem[2]; int active; wait_queue_head_t wait; } runlist; struct { - struct nouveau_gpuobj *mem; - struct nouveau_vma bar; + struct nvkm_gpuobj *mem; + struct nvkm_vma bar; } user; int spoon_nr; }; -struct nvc0_fifo_base { - struct nouveau_fifo_base base; - struct nouveau_gpuobj *pgd; - struct nouveau_vm *vm; +struct gf100_fifo_base { + struct nvkm_fifo_base base; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; }; -struct nvc0_fifo_chan { - struct nouveau_fifo_chan base; +struct gf100_fifo_chan { + struct nvkm_fifo_chan base; enum { STOPPED, RUNNING, @@ -79,10 +74,10 @@ struct nvc0_fifo_chan { ******************************************************************************/ static void -nvc0_fifo_runlist_update(struct nvc0_fifo_priv *priv) +gf100_fifo_runlist_update(struct gf100_fifo_priv *priv) { - struct nouveau_bar *bar = nouveau_bar(priv); - struct nouveau_gpuobj *cur; + struct nvkm_bar *bar = nvkm_bar(priv); + struct nvkm_gpuobj *cur; int i, p; mutex_lock(&nv_subdev(priv)->mutex); @@ -90,7 +85,7 @@ nvc0_fifo_runlist_update(struct nvc0_fifo_priv *priv) priv->runlist.active = !priv->runlist.active; for (i = 0, p = 0; i < 128; i++) { - struct nvc0_fifo_chan *chan = (void *)priv->base.channel[i]; + struct gf100_fifo_chan *chan = (void *)priv->base.channel[i]; if (chan && chan->state == RUNNING) { nv_wo32(cur, p + 0, i); nv_wo32(cur, p + 4, 0x00000004); @@ -110,12 +105,12 @@ nvc0_fifo_runlist_update(struct nvc0_fifo_priv *priv) } static int -nvc0_fifo_context_attach(struct nouveau_object *parent, - struct nouveau_object *object) +gf100_fifo_context_attach(struct nvkm_object *parent, + struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(parent); - struct nvc0_fifo_base *base = (void *)parent->parent; - struct nouveau_engctx *ectx = (void *)object; + struct nvkm_bar *bar = nvkm_bar(parent); + struct gf100_fifo_base *base = (void *)parent->parent; + struct nvkm_engctx *ectx = (void *)object; u32 addr; int ret; @@ -132,8 +127,8 @@ nvc0_fifo_context_attach(struct nouveau_object *parent, } if (!ectx->vma.node) { - ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, - NV_MEM_ACCESS_RW, &ectx->vma); + ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, + NV_MEM_ACCESS_RW, &ectx->vma); if (ret) return ret; @@ -147,13 +142,13 @@ nvc0_fifo_context_attach(struct nouveau_object *parent, } static int -nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend, - struct nouveau_object *object) +gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend, + struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(parent); - struct nvc0_fifo_priv *priv = (void *)parent->engine; - struct nvc0_fifo_base *base = (void *)parent->parent; - struct nvc0_fifo_chan *chan = (void *)parent; + struct nvkm_bar *bar = nvkm_bar(parent); + struct gf100_fifo_priv *priv = (void *)parent->engine; + struct gf100_fifo_base *base = (void *)parent->parent; + struct gf100_fifo_chan *chan = (void *)parent; u32 addr; switch (nv_engidx(object->engine)) { @@ -171,7 +166,7 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend, nv_wr32(priv, 0x002634, chan->base.chid); if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { nv_error(priv, "channel %d [%s] kick timeout\n", - chan->base.chid, nouveau_client_name(chan)); + chan->base.chid, nvkm_client_name(chan)); if (suspend) return -EBUSY; } @@ -183,18 +178,17 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend, } static int -nvc0_fifo_chan_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv50_channel_gpfifo_v0 v0; } *args = data; - struct nouveau_bar *bar = nouveau_bar(parent); - struct nvc0_fifo_priv *priv = (void *)engine; - struct nvc0_fifo_base *base = (void *)parent; - struct nvc0_fifo_chan *chan; + struct nvkm_bar *bar = nvkm_bar(parent); + struct gf100_fifo_priv *priv = (void *)engine; + struct gf100_fifo_base *base = (void *)parent; + struct gf100_fifo_chan *chan; u64 usermem, ioffset, ilength; int ret, i; @@ -207,24 +201,24 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 1, - priv->user.bar.offset, 0x1000, - args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_CE0) | - (1ULL << NVDEV_ENGINE_CE1) | - (1ULL << NVDEV_ENGINE_MSVLD) | - (1ULL << NVDEV_ENGINE_MSPDEC) | - (1ULL << NVDEV_ENGINE_MSPPP), &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, + priv->user.bar.offset, 0x1000, + args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_CE0) | + (1ULL << NVDEV_ENGINE_CE1) | + (1ULL << NVDEV_ENGINE_MSVLD) | + (1ULL << NVDEV_ENGINE_MSPDEC) | + (1ULL << NVDEV_ENGINE_MSPPP), &chan); *pobject = nv_object(chan); if (ret) return ret; args->v0.chid = chan->base.chid; - nv_parent(chan)->context_attach = nvc0_fifo_context_attach; - nv_parent(chan)->context_detach = nvc0_fifo_context_detach; + nv_parent(chan)->context_attach = gf100_fifo_context_attach; + nv_parent(chan)->context_detach = gf100_fifo_context_detach; usermem = chan->base.chid * 0x1000; ioffset = args->v0.ioffset; @@ -254,15 +248,15 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent, } static int -nvc0_fifo_chan_init(struct nouveau_object *object) +gf100_fifo_chan_init(struct nvkm_object *object) { - struct nouveau_gpuobj *base = nv_gpuobj(object->parent); - struct nvc0_fifo_priv *priv = (void *)object->engine; - struct nvc0_fifo_chan *chan = (void *)object; + struct nvkm_gpuobj *base = nv_gpuobj(object->parent); + struct gf100_fifo_priv *priv = (void *)object->engine; + struct gf100_fifo_chan *chan = (void *)object; u32 chid = chan->base.chid; int ret; - ret = nouveau_fifo_channel_init(&chan->base); + ret = nvkm_fifo_channel_init(&chan->base); if (ret) return ret; @@ -270,47 +264,47 @@ nvc0_fifo_chan_init(struct nouveau_object *object) if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001); - nvc0_fifo_runlist_update(priv); + gf100_fifo_runlist_update(priv); } return 0; } -static void nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv); +static void gf100_fifo_intr_engine(struct gf100_fifo_priv *priv); static int -nvc0_fifo_chan_fini(struct nouveau_object *object, bool suspend) +gf100_fifo_chan_fini(struct nvkm_object *object, bool suspend) { - struct nvc0_fifo_priv *priv = (void *)object->engine; - struct nvc0_fifo_chan *chan = (void *)object; + struct gf100_fifo_priv *priv = (void *)object->engine; + struct gf100_fifo_chan *chan = (void *)object; u32 chid = chan->base.chid; if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000); - nvc0_fifo_runlist_update(priv); + gf100_fifo_runlist_update(priv); } - nvc0_fifo_intr_engine(priv); + gf100_fifo_intr_engine(priv); nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000); - return nouveau_fifo_channel_fini(&chan->base, suspend); + return nvkm_fifo_channel_fini(&chan->base, suspend); } -static struct nouveau_ofuncs -nvc0_fifo_ofuncs = { - .ctor = nvc0_fifo_chan_ctor, - .dtor = _nouveau_fifo_channel_dtor, - .init = nvc0_fifo_chan_init, - .fini = nvc0_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy +static struct nvkm_ofuncs +gf100_fifo_ofuncs = { + .ctor = gf100_fifo_chan_ctor, + .dtor = _nvkm_fifo_channel_dtor, + .init = gf100_fifo_chan_init, + .fini = gf100_fifo_chan_fini, + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_oclass -nvc0_fifo_sclass[] = { - { FERMI_CHANNEL_GPFIFO, &nvc0_fifo_ofuncs }, +static struct nvkm_oclass +gf100_fifo_sclass[] = { + { FERMI_CHANNEL_GPFIFO, &gf100_fifo_ofuncs }, {} }; @@ -319,23 +313,22 @@ nvc0_fifo_sclass[] = { ******************************************************************************/ static int -nvc0_fifo_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nvc0_fifo_base *base; + struct gf100_fifo_base *base; int ret; - ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_HEAP, &base); + ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_HEAP, &base); *pobject = nv_object(base); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, - &base->pgd); + ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, + &base->pgd); if (ret) return ret; @@ -344,7 +337,7 @@ nvc0_fifo_context_ctor(struct nouveau_object *parent, nv_wo32(base, 0x0208, 0xffffffff); nv_wo32(base, 0x020c, 0x000000ff); - ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd); + ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); if (ret) return ret; @@ -352,24 +345,24 @@ nvc0_fifo_context_ctor(struct nouveau_object *parent, } static void -nvc0_fifo_context_dtor(struct nouveau_object *object) +gf100_fifo_context_dtor(struct nvkm_object *object) { - struct nvc0_fifo_base *base = (void *)object; - nouveau_vm_ref(NULL, &base->vm, base->pgd); - nouveau_gpuobj_ref(NULL, &base->pgd); - nouveau_fifo_context_destroy(&base->base); + struct gf100_fifo_base *base = (void *)object; + nvkm_vm_ref(NULL, &base->vm, base->pgd); + nvkm_gpuobj_ref(NULL, &base->pgd); + nvkm_fifo_context_destroy(&base->base); } -static struct nouveau_oclass -nvc0_fifo_cclass = { +static struct nvkm_oclass +gf100_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_fifo_context_ctor, - .dtor = nvc0_fifo_context_dtor, - .init = _nouveau_fifo_context_init, - .fini = _nouveau_fifo_context_fini, - .rd32 = _nouveau_fifo_context_rd32, - .wr32 = _nouveau_fifo_context_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_fifo_context_ctor, + .dtor = gf100_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, }, }; @@ -378,7 +371,7 @@ nvc0_fifo_cclass = { ******************************************************************************/ static inline int -nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn) +gf100_fifo_engidx(struct gf100_fifo_priv *priv, u32 engn) { switch (engn) { case NVDEV_ENGINE_GR : engn = 0; break; @@ -394,8 +387,8 @@ nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn) return engn; } -static inline struct nouveau_engine * -nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn) +static inline struct nvkm_engine * +gf100_fifo_engine(struct gf100_fifo_priv *priv, u32 engn) { switch (engn) { case 0: engn = NVDEV_ENGINE_GR; break; @@ -408,14 +401,14 @@ nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn) return NULL; } - return nouveau_engine(priv, engn); + return nvkm_engine(priv, engn); } static void -nvc0_fifo_recover_work(struct work_struct *work) +gf100_fifo_recover_work(struct work_struct *work) { - struct nvc0_fifo_priv *priv = container_of(work, typeof(*priv), fault); - struct nouveau_object *engine; + struct gf100_fifo_priv *priv = container_of(work, typeof(*priv), fault); + struct nvkm_object *engine; unsigned long flags; u32 engn, engm = 0; u64 mask, todo; @@ -426,24 +419,24 @@ nvc0_fifo_recover_work(struct work_struct *work) spin_unlock_irqrestore(&priv->base.lock, flags); for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) - engm |= 1 << nvc0_fifo_engidx(priv, engn); + engm |= 1 << gf100_fifo_engidx(priv, engn); nv_mask(priv, 0x002630, engm, engm); for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { - if ((engine = (void *)nouveau_engine(priv, engn))) { + if ((engine = (void *)nvkm_engine(priv, engn))) { nv_ofuncs(engine)->fini(engine, false); WARN_ON(nv_ofuncs(engine)->init(engine)); } } - nvc0_fifo_runlist_update(priv); + gf100_fifo_runlist_update(priv); nv_wr32(priv, 0x00262c, engm); nv_mask(priv, 0x002630, engm, 0x00000000); } static void -nvc0_fifo_recover(struct nvc0_fifo_priv *priv, struct nouveau_engine *engine, - struct nvc0_fifo_chan *chan) +gf100_fifo_recover(struct gf100_fifo_priv *priv, struct nvkm_engine *engine, + struct gf100_fifo_chan *chan) { u32 chid = chan->base.chid; unsigned long flags; @@ -461,10 +454,10 @@ nvc0_fifo_recover(struct nvc0_fifo_priv *priv, struct nouveau_engine *engine, } static int -nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data) +gf100_fifo_swmthd(struct gf100_fifo_priv *priv, u32 chid, u32 mthd, u32 data) { - struct nvc0_fifo_chan *chan = NULL; - struct nouveau_handle *bind; + struct gf100_fifo_chan *chan = NULL; + struct nvkm_handle *bind; unsigned long flags; int ret = -EINVAL; @@ -474,11 +467,11 @@ nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data) if (unlikely(!chan)) goto out; - bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e); + bind = nvkm_namedb_get_class(nv_namedb(chan), 0x906e); if (likely(bind)) { if (!mthd || !nv_call(bind->object, mthd, data)) ret = 0; - nouveau_namedb_put(bind); + nvkm_namedb_put(bind); } out: @@ -486,17 +479,17 @@ out: return ret; } -static const struct nouveau_enum -nvc0_fifo_sched_reason[] = { +static const struct nvkm_enum +gf100_fifo_sched_reason[] = { { 0x0a, "CTXSW_TIMEOUT" }, {} }; static void -nvc0_fifo_intr_sched_ctxsw(struct nvc0_fifo_priv *priv) +gf100_fifo_intr_sched_ctxsw(struct gf100_fifo_priv *priv) { - struct nouveau_engine *engine; - struct nvc0_fifo_chan *chan; + struct nvkm_engine *engine; + struct gf100_fifo_chan *chan; u32 engn; for (engn = 0; engn < 6; engn++) { @@ -511,22 +504,22 @@ nvc0_fifo_intr_sched_ctxsw(struct nvc0_fifo_priv *priv) if (busy && unk0 && unk1) { if (!(chan = (void *)priv->base.channel[chid])) continue; - if (!(engine = nvc0_fifo_engine(priv, engn))) + if (!(engine = gf100_fifo_engine(priv, engn))) continue; - nvc0_fifo_recover(priv, engine, chan); + gf100_fifo_recover(priv, engine, chan); } } } static void -nvc0_fifo_intr_sched(struct nvc0_fifo_priv *priv) +gf100_fifo_intr_sched(struct gf100_fifo_priv *priv) { u32 intr = nv_rd32(priv, 0x00254c); u32 code = intr & 0x000000ff; - const struct nouveau_enum *en; + const struct nvkm_enum *en; char enunk[6] = ""; - en = nouveau_enum_find(nvc0_fifo_sched_reason, code); + en = nvkm_enum_find(gf100_fifo_sched_reason, code); if (!en) snprintf(enunk, sizeof(enunk), "UNK%02x", code); @@ -534,15 +527,15 @@ nvc0_fifo_intr_sched(struct nvc0_fifo_priv *priv) switch (code) { case 0x0a: - nvc0_fifo_intr_sched_ctxsw(priv); + gf100_fifo_intr_sched_ctxsw(priv); break; default: break; } } -static const struct nouveau_enum -nvc0_fifo_fault_engine[] = { +static const struct nvkm_enum +gf100_fifo_fault_engine[] = { { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR }, { 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB }, { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, @@ -558,8 +551,8 @@ nvc0_fifo_fault_engine[] = { {} }; -static const struct nouveau_enum -nvc0_fifo_fault_reason[] = { +static const struct nvkm_enum +gf100_fifo_fault_reason[] = { { 0x00, "PT_NOT_PRESENT" }, { 0x01, "PT_TOO_SHORT" }, { 0x02, "PAGE_NOT_PRESENT" }, @@ -572,8 +565,8 @@ nvc0_fifo_fault_reason[] = { {} }; -static const struct nouveau_enum -nvc0_fifo_fault_hubclient[] = { +static const struct nvkm_enum +gf100_fifo_fault_hubclient[] = { { 0x01, "PCOPY0" }, { 0x02, "PCOPY1" }, { 0x04, "DISPATCH" }, @@ -591,8 +584,8 @@ nvc0_fifo_fault_hubclient[] = { {} }; -static const struct nouveau_enum -nvc0_fifo_fault_gpcclient[] = { +static const struct nvkm_enum +gf100_fifo_fault_gpcclient[] = { { 0x01, "TEX" }, { 0x0c, "ESETUP" }, { 0x0e, "CTXCTL" }, @@ -601,7 +594,7 @@ nvc0_fifo_fault_gpcclient[] = { }; static void -nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit) +gf100_fifo_intr_fault(struct gf100_fifo_priv *priv, int unit) { u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10)); u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10)); @@ -612,19 +605,19 @@ nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit) u32 write = (stat & 0x00000080); u32 hub = (stat & 0x00000040); u32 reason = (stat & 0x0000000f); - struct nouveau_object *engctx = NULL, *object; - struct nouveau_engine *engine = NULL; - const struct nouveau_enum *er, *eu, *ec; + struct nvkm_object *engctx = NULL, *object; + struct nvkm_engine *engine = NULL; + const struct nvkm_enum *er, *eu, *ec; char erunk[6] = ""; char euunk[6] = ""; char ecunk[6] = ""; char gpcid[3] = ""; - er = nouveau_enum_find(nvc0_fifo_fault_reason, reason); + er = nvkm_enum_find(gf100_fifo_fault_reason, reason); if (!er) snprintf(erunk, sizeof(erunk), "UNK%02X", reason); - eu = nouveau_enum_find(nvc0_fifo_fault_engine, unit); + eu = nvkm_enum_find(gf100_fifo_fault_engine, unit); if (eu) { switch (eu->data2) { case NVDEV_SUBDEV_BAR: @@ -637,9 +630,9 @@ nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit) nv_mask(priv, 0x001718, 0x00000000, 0x00000000); break; default: - engine = nouveau_engine(priv, eu->data2); + engine = nvkm_engine(priv, eu->data2); if (engine) - engctx = nouveau_engctx_get(engine, inst); + engctx = nvkm_engctx_get(engine, inst); break; } } else { @@ -647,9 +640,9 @@ nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit) } if (hub) { - ec = nouveau_enum_find(nvc0_fifo_fault_hubclient, client); + ec = nvkm_enum_find(gf100_fifo_fault_hubclient, client); } else { - ec = nouveau_enum_find(nvc0_fifo_fault_gpcclient, client); + ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, client); snprintf(gpcid, sizeof(gpcid), "%d", gpc); } @@ -661,23 +654,23 @@ nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit) (u64)vahi << 32 | valo, er ? er->name : erunk, eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/", ec ? ec->name : ecunk, (u64)inst << 12, - nouveau_client_name(engctx)); + nvkm_client_name(engctx)); object = engctx; while (object) { switch (nv_mclass(object)) { case FERMI_CHANNEL_GPFIFO: - nvc0_fifo_recover(priv, engine, (void *)object); + gf100_fifo_recover(priv, engine, (void *)object); break; } object = object->parent; } - nouveau_engctx_put(engctx); + nvkm_engctx_put(engctx); } -static const struct nouveau_bitfield -nvc0_fifo_pbdma_intr[] = { +static const struct nvkm_bitfield +gf100_fifo_pbdma_intr[] = { /* { 0x00008000, "" } seen with null ib push */ { 0x00200000, "ILLEGAL_MTHD" }, { 0x00800000, "EMPTY_SUBC" }, @@ -685,7 +678,7 @@ nvc0_fifo_pbdma_intr[] = { }; static void -nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv *priv, int unit) +gf100_fifo_intr_pbdma(struct gf100_fifo_priv *priv, int unit) { u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)); u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000)); @@ -696,18 +689,18 @@ nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv *priv, int unit) u32 show = stat; if (stat & 0x00800000) { - if (!nvc0_fifo_swmthd(priv, chid, mthd, data)) + if (!gf100_fifo_swmthd(priv, chid, mthd, data)) show &= ~0x00800000; } if (show) { nv_error(priv, "PBDMA%d:", unit); - nouveau_bitfield_print(nvc0_fifo_pbdma_intr, show); + nvkm_bitfield_print(gf100_fifo_pbdma_intr, show); pr_cont("\n"); nv_error(priv, "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", unit, chid, - nouveau_client_name_for_fifo_chid(&priv->base, chid), + nvkm_client_name_for_fifo_chid(&priv->base, chid), subc, mthd, data); } @@ -716,7 +709,7 @@ nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv *priv, int unit) } static void -nvc0_fifo_intr_runlist(struct nvc0_fifo_priv *priv) +gf100_fifo_intr_runlist(struct gf100_fifo_priv *priv) { u32 intr = nv_rd32(priv, 0x002a00); @@ -733,7 +726,7 @@ nvc0_fifo_intr_runlist(struct nvc0_fifo_priv *priv) } static void -nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn) +gf100_fifo_intr_engine_unit(struct gf100_fifo_priv *priv, int engn) { u32 intr = nv_rd32(priv, 0x0025a8 + (engn * 0x04)); u32 inte = nv_rd32(priv, 0x002628); @@ -744,7 +737,7 @@ nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn) for (unkn = 0; unkn < 8; unkn++) { u32 ints = (intr >> (unkn * 0x04)) & inte; if (ints & 0x1) { - nouveau_fifo_uevent(&priv->base); + nvkm_fifo_uevent(&priv->base); ints &= ~1; } if (ints) { @@ -755,20 +748,20 @@ nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn) } static void -nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv) +gf100_fifo_intr_engine(struct gf100_fifo_priv *priv) { u32 mask = nv_rd32(priv, 0x0025a4); while (mask) { u32 unit = __ffs(mask); - nvc0_fifo_intr_engine_unit(priv, unit); + gf100_fifo_intr_engine_unit(priv, unit); mask &= ~(1 << unit); } } static void -nvc0_fifo_intr(struct nouveau_subdev *subdev) +gf100_fifo_intr(struct nvkm_subdev *subdev) { - struct nvc0_fifo_priv *priv = (void *)subdev; + struct gf100_fifo_priv *priv = (void *)subdev; u32 mask = nv_rd32(priv, 0x002140); u32 stat = nv_rd32(priv, 0x002100) & mask; @@ -780,7 +773,7 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev) } if (stat & 0x00000100) { - nvc0_fifo_intr_sched(priv); + gf100_fifo_intr_sched(priv); nv_wr32(priv, 0x002100, 0x00000100); stat &= ~0x00000100; } @@ -803,7 +796,7 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev) u32 mask = nv_rd32(priv, 0x00259c); while (mask) { u32 unit = __ffs(mask); - nvc0_fifo_intr_fault(priv, unit); + gf100_fifo_intr_fault(priv, unit); nv_wr32(priv, 0x00259c, (1 << unit)); mask &= ~(1 << unit); } @@ -814,7 +807,7 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev) u32 mask = nv_rd32(priv, 0x0025a0); while (mask) { u32 unit = __ffs(mask); - nvc0_fifo_intr_pbdma(priv, unit); + gf100_fifo_intr_pbdma(priv, unit); nv_wr32(priv, 0x0025a0, (1 << unit)); mask &= ~(1 << unit); } @@ -822,12 +815,12 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev) } if (stat & 0x40000000) { - nvc0_fifo_intr_runlist(priv); + gf100_fifo_intr_runlist(priv); stat &= ~0x40000000; } if (stat & 0x80000000) { - nvc0_fifo_intr_engine(priv); + gf100_fifo_intr_engine(priv); stat &= ~0x80000000; } @@ -839,94 +832,94 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev) } static void -nvc0_fifo_uevent_init(struct nvkm_event *event, int type, int index) +gf100_fifo_uevent_init(struct nvkm_event *event, int type, int index) { - struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); nv_mask(fifo, 0x002140, 0x80000000, 0x80000000); } static void -nvc0_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +gf100_fifo_uevent_fini(struct nvkm_event *event, int type, int index) { - struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); nv_mask(fifo, 0x002140, 0x80000000, 0x00000000); } static const struct nvkm_event_func -nvc0_fifo_uevent_func = { - .ctor = nouveau_fifo_uevent_ctor, - .init = nvc0_fifo_uevent_init, - .fini = nvc0_fifo_uevent_fini, +gf100_fifo_uevent_func = { + .ctor = nvkm_fifo_uevent_ctor, + .init = gf100_fifo_uevent_init, + .fini = gf100_fifo_uevent_fini, }; static int -nvc0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nvc0_fifo_priv *priv; + struct gf100_fifo_priv *priv; int ret; - ret = nouveau_fifo_create(parent, engine, oclass, 0, 127, &priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &priv); *pobject = nv_object(priv); if (ret) return ret; - INIT_WORK(&priv->fault, nvc0_fifo_recover_work); + INIT_WORK(&priv->fault, gf100_fifo_recover_work); - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, - &priv->runlist.mem[0]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, + &priv->runlist.mem[0]); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, - &priv->runlist.mem[1]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, + &priv->runlist.mem[1]); if (ret) return ret; init_waitqueue_head(&priv->runlist.wait); - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0, - &priv->user.mem); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0, + &priv->user.mem); if (ret) return ret; - ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, - &priv->user.bar); + ret = nvkm_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, + &priv->user.bar); if (ret) return ret; - ret = nvkm_event_init(&nvc0_fifo_uevent_func, 1, 1, &priv->base.uevent); + ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &priv->base.uevent); if (ret) return ret; nv_subdev(priv)->unit = 0x00000100; - nv_subdev(priv)->intr = nvc0_fifo_intr; - nv_engine(priv)->cclass = &nvc0_fifo_cclass; - nv_engine(priv)->sclass = nvc0_fifo_sclass; + nv_subdev(priv)->intr = gf100_fifo_intr; + nv_engine(priv)->cclass = &gf100_fifo_cclass; + nv_engine(priv)->sclass = gf100_fifo_sclass; return 0; } static void -nvc0_fifo_dtor(struct nouveau_object *object) +gf100_fifo_dtor(struct nvkm_object *object) { - struct nvc0_fifo_priv *priv = (void *)object; + struct gf100_fifo_priv *priv = (void *)object; - nouveau_gpuobj_unmap(&priv->user.bar); - nouveau_gpuobj_ref(NULL, &priv->user.mem); - nouveau_gpuobj_ref(NULL, &priv->runlist.mem[0]); - nouveau_gpuobj_ref(NULL, &priv->runlist.mem[1]); + nvkm_gpuobj_unmap(&priv->user.bar); + nvkm_gpuobj_ref(NULL, &priv->user.mem); + nvkm_gpuobj_ref(NULL, &priv->runlist.mem[0]); + nvkm_gpuobj_ref(NULL, &priv->runlist.mem[1]); - nouveau_fifo_destroy(&priv->base); + nvkm_fifo_destroy(&priv->base); } static int -nvc0_fifo_init(struct nouveau_object *object) +gf100_fifo_init(struct nvkm_object *object) { - struct nvc0_fifo_priv *priv = (void *)object; + struct gf100_fifo_priv *priv = (void *)object; int ret, i; - ret = nouveau_fifo_init(&priv->base); + ret = nvkm_fifo_init(&priv->base); if (ret) return ret; @@ -962,13 +955,13 @@ nvc0_fifo_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * -nvc0_fifo_oclass = &(struct nouveau_oclass) { +struct nvkm_oclass * +gf100_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_fifo_ctor, - .dtor = nvc0_fifo_dtor, - .init = nvc0_fifo_init, - .fini = _nouveau_fifo_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_fifo_ctor, + .dtor = gf100_fifo_dtor, + .init = gf100_fifo_init, + .fini = _nvkm_fifo_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index f5965eb6b262..9585539e59f2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -21,25 +21,19 @@ * * Authors: Ben Skeggs */ +#include "gk104.h" #include <core/client.h> -#include <core/handle.h> -#include <core/namedb.h> -#include <core/gpuobj.h> #include <core/engctx.h> -#include <core/event.h> -#include <nvif/unpack.h> -#include <nvif/class.h> #include <core/enum.h> - -#include <subdev/timer.h> +#include <core/handle.h> #include <subdev/bar.h> #include <subdev/fb.h> #include <subdev/mmu.h> +#include <subdev/timer.h> -#include <engine/dmaobj.h> - -#include "nve0.h" +#include <nvif/class.h> +#include <nvif/unpack.h> #define _(a,b) { (a), ((1ULL << (a)) | (b)) } static const struct { @@ -58,34 +52,34 @@ static const struct { #undef _ #define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine) -struct nve0_fifo_engn { - struct nouveau_gpuobj *runlist[2]; +struct gk104_fifo_engn { + struct nvkm_gpuobj *runlist[2]; int cur_runlist; wait_queue_head_t wait; }; -struct nve0_fifo_priv { - struct nouveau_fifo base; +struct gk104_fifo_priv { + struct nvkm_fifo base; struct work_struct fault; u64 mask; - struct nve0_fifo_engn engine[FIFO_ENGINE_NR]; + struct gk104_fifo_engn engine[FIFO_ENGINE_NR]; struct { - struct nouveau_gpuobj *mem; - struct nouveau_vma bar; + struct nvkm_gpuobj *mem; + struct nvkm_vma bar; } user; int spoon_nr; }; -struct nve0_fifo_base { - struct nouveau_fifo_base base; - struct nouveau_gpuobj *pgd; - struct nouveau_vm *vm; +struct gk104_fifo_base { + struct nvkm_fifo_base base; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; }; -struct nve0_fifo_chan { - struct nouveau_fifo_chan base; +struct gk104_fifo_chan { + struct nvkm_fifo_chan base; u32 engine; enum { STOPPED, @@ -99,11 +93,11 @@ struct nve0_fifo_chan { ******************************************************************************/ static void -nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine) +gk104_fifo_runlist_update(struct gk104_fifo_priv *priv, u32 engine) { - struct nouveau_bar *bar = nouveau_bar(priv); - struct nve0_fifo_engn *engn = &priv->engine[engine]; - struct nouveau_gpuobj *cur; + struct nvkm_bar *bar = nvkm_bar(priv); + struct gk104_fifo_engn *engn = &priv->engine[engine]; + struct nvkm_gpuobj *cur; int i, p; mutex_lock(&nv_subdev(priv)->mutex); @@ -111,7 +105,7 @@ nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine) engn->cur_runlist = !engn->cur_runlist; for (i = 0, p = 0; i < priv->base.max; i++) { - struct nve0_fifo_chan *chan = (void *)priv->base.channel[i]; + struct gk104_fifo_chan *chan = (void *)priv->base.channel[i]; if (chan && chan->state == RUNNING && chan->engine == engine) { nv_wo32(cur, p + 0, i); nv_wo32(cur, p + 4, 0x00000000); @@ -131,12 +125,12 @@ nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine) } static int -nve0_fifo_context_attach(struct nouveau_object *parent, - struct nouveau_object *object) +gk104_fifo_context_attach(struct nvkm_object *parent, + struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(parent); - struct nve0_fifo_base *base = (void *)parent->parent; - struct nouveau_engctx *ectx = (void *)object; + struct nvkm_bar *bar = nvkm_bar(parent); + struct gk104_fifo_base *base = (void *)parent->parent; + struct nvkm_engctx *ectx = (void *)object; u32 addr; int ret; @@ -157,8 +151,8 @@ nve0_fifo_context_attach(struct nouveau_object *parent, } if (!ectx->vma.node) { - ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, - NV_MEM_ACCESS_RW, &ectx->vma); + ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, + NV_MEM_ACCESS_RW, &ectx->vma); if (ret) return ret; @@ -172,13 +166,13 @@ nve0_fifo_context_attach(struct nouveau_object *parent, } static int -nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend, - struct nouveau_object *object) +gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend, + struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(parent); - struct nve0_fifo_priv *priv = (void *)parent->engine; - struct nve0_fifo_base *base = (void *)parent->parent; - struct nve0_fifo_chan *chan = (void *)parent; + struct nvkm_bar *bar = nvkm_bar(parent); + struct gk104_fifo_priv *priv = (void *)parent->engine; + struct gk104_fifo_base *base = (void *)parent->parent; + struct gk104_fifo_chan *chan = (void *)parent; u32 addr; switch (nv_engidx(object->engine)) { @@ -197,7 +191,7 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend, nv_wr32(priv, 0x002634, chan->base.chid); if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { nv_error(priv, "channel %d [%s] kick timeout\n", - chan->base.chid, nouveau_client_name(chan)); + chan->base.chid, nvkm_client_name(chan)); if (suspend) return -EBUSY; } @@ -212,18 +206,17 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend, } static int -nve0_fifo_chan_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct kepler_channel_gpfifo_a_v0 v0; } *args = data; - struct nouveau_bar *bar = nouveau_bar(parent); - struct nve0_fifo_priv *priv = (void *)engine; - struct nve0_fifo_base *base = (void *)parent; - struct nve0_fifo_chan *chan; + struct nvkm_bar *bar = nvkm_bar(parent); + struct gk104_fifo_priv *priv = (void *)engine; + struct gk104_fifo_base *base = (void *)parent; + struct gk104_fifo_chan *chan; u64 usermem, ioffset, ilength; int ret, i; @@ -238,7 +231,7 @@ nve0_fifo_chan_ctor(struct nouveau_object *parent, for (i = 0; i < FIFO_ENGINE_NR; i++) { if (args->v0.engine & (1 << i)) { - if (nouveau_engine(parent, fifo_engine[i].subdev)) { + if (nvkm_engine(parent, fifo_engine[i].subdev)) { args->v0.engine = (1 << i); break; } @@ -250,18 +243,18 @@ nve0_fifo_chan_ctor(struct nouveau_object *parent, return -ENODEV; } - ret = nouveau_fifo_channel_create(parent, engine, oclass, 1, - priv->user.bar.offset, 0x200, - args->v0.pushbuf, - fifo_engine[i].mask, &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, + priv->user.bar.offset, 0x200, + args->v0.pushbuf, + fifo_engine[i].mask, &chan); *pobject = nv_object(chan); if (ret) return ret; args->v0.chid = chan->base.chid; - nv_parent(chan)->context_attach = nve0_fifo_context_attach; - nv_parent(chan)->context_detach = nve0_fifo_context_detach; + nv_parent(chan)->context_attach = gk104_fifo_context_attach; + nv_parent(chan)->context_detach = gk104_fifo_context_detach; chan->engine = i; usermem = chan->base.chid * 0x200; @@ -290,15 +283,15 @@ nve0_fifo_chan_ctor(struct nouveau_object *parent, } static int -nve0_fifo_chan_init(struct nouveau_object *object) +gk104_fifo_chan_init(struct nvkm_object *object) { - struct nouveau_gpuobj *base = nv_gpuobj(object->parent); - struct nve0_fifo_priv *priv = (void *)object->engine; - struct nve0_fifo_chan *chan = (void *)object; + struct nvkm_gpuobj *base = nv_gpuobj(object->parent); + struct gk104_fifo_priv *priv = (void *)object->engine; + struct gk104_fifo_chan *chan = (void *)object; u32 chid = chan->base.chid; int ret; - ret = nouveau_fifo_channel_init(&chan->base); + ret = nvkm_fifo_channel_init(&chan->base); if (ret) return ret; @@ -307,7 +300,7 @@ nve0_fifo_chan_init(struct nouveau_object *object) if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); - nve0_fifo_runlist_update(priv, chan->engine); + gk104_fifo_runlist_update(priv, chan->engine); nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); } @@ -315,36 +308,36 @@ nve0_fifo_chan_init(struct nouveau_object *object) } static int -nve0_fifo_chan_fini(struct nouveau_object *object, bool suspend) +gk104_fifo_chan_fini(struct nvkm_object *object, bool suspend) { - struct nve0_fifo_priv *priv = (void *)object->engine; - struct nve0_fifo_chan *chan = (void *)object; + struct gk104_fifo_priv *priv = (void *)object->engine; + struct gk104_fifo_chan *chan = (void *)object; u32 chid = chan->base.chid; if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800); - nve0_fifo_runlist_update(priv, chan->engine); + gk104_fifo_runlist_update(priv, chan->engine); } nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000); - return nouveau_fifo_channel_fini(&chan->base, suspend); + return nvkm_fifo_channel_fini(&chan->base, suspend); } -static struct nouveau_ofuncs -nve0_fifo_ofuncs = { - .ctor = nve0_fifo_chan_ctor, - .dtor = _nouveau_fifo_channel_dtor, - .init = nve0_fifo_chan_init, - .fini = nve0_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy +static struct nvkm_ofuncs +gk104_fifo_ofuncs = { + .ctor = gk104_fifo_chan_ctor, + .dtor = _nvkm_fifo_channel_dtor, + .init = gk104_fifo_chan_init, + .fini = gk104_fifo_chan_fini, + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_oclass -nve0_fifo_sclass[] = { - { KEPLER_CHANNEL_GPFIFO_A, &nve0_fifo_ofuncs }, +static struct nvkm_oclass +gk104_fifo_sclass[] = { + { KEPLER_CHANNEL_GPFIFO_A, &gk104_fifo_ofuncs }, {} }; @@ -353,22 +346,21 @@ nve0_fifo_sclass[] = { ******************************************************************************/ static int -nve0_fifo_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk104_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nve0_fifo_base *base; + struct gk104_fifo_base *base; int ret; - ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base); + ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base); *pobject = nv_object(base); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, - &base->pgd); + ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, + &base->pgd); if (ret) return ret; @@ -377,7 +369,7 @@ nve0_fifo_context_ctor(struct nouveau_object *parent, nv_wo32(base, 0x0208, 0xffffffff); nv_wo32(base, 0x020c, 0x000000ff); - ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd); + ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); if (ret) return ret; @@ -385,24 +377,24 @@ nve0_fifo_context_ctor(struct nouveau_object *parent, } static void -nve0_fifo_context_dtor(struct nouveau_object *object) +gk104_fifo_context_dtor(struct nvkm_object *object) { - struct nve0_fifo_base *base = (void *)object; - nouveau_vm_ref(NULL, &base->vm, base->pgd); - nouveau_gpuobj_ref(NULL, &base->pgd); - nouveau_fifo_context_destroy(&base->base); + struct gk104_fifo_base *base = (void *)object; + nvkm_vm_ref(NULL, &base->vm, base->pgd); + nvkm_gpuobj_ref(NULL, &base->pgd); + nvkm_fifo_context_destroy(&base->base); } -static struct nouveau_oclass -nve0_fifo_cclass = { +static struct nvkm_oclass +gk104_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_fifo_context_ctor, - .dtor = nve0_fifo_context_dtor, - .init = _nouveau_fifo_context_init, - .fini = _nouveau_fifo_context_fini, - .rd32 = _nouveau_fifo_context_rd32, - .wr32 = _nouveau_fifo_context_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_fifo_context_ctor, + .dtor = gk104_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, }, }; @@ -411,7 +403,7 @@ nve0_fifo_cclass = { ******************************************************************************/ static inline int -nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn) +gk104_fifo_engidx(struct gk104_fifo_priv *priv, u32 engn) { switch (engn) { case NVDEV_ENGINE_GR : @@ -429,19 +421,19 @@ nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn) return engn; } -static inline struct nouveau_engine * -nve0_fifo_engine(struct nve0_fifo_priv *priv, u32 engn) +static inline struct nvkm_engine * +gk104_fifo_engine(struct gk104_fifo_priv *priv, u32 engn) { if (engn >= ARRAY_SIZE(fifo_engine)) return NULL; - return nouveau_engine(priv, fifo_engine[engn].subdev); + return nvkm_engine(priv, fifo_engine[engn].subdev); } static void -nve0_fifo_recover_work(struct work_struct *work) +gk104_fifo_recover_work(struct work_struct *work) { - struct nve0_fifo_priv *priv = container_of(work, typeof(*priv), fault); - struct nouveau_object *engine; + struct gk104_fifo_priv *priv = container_of(work, typeof(*priv), fault); + struct nvkm_object *engine; unsigned long flags; u32 engn, engm = 0; u64 mask, todo; @@ -452,15 +444,15 @@ nve0_fifo_recover_work(struct work_struct *work) spin_unlock_irqrestore(&priv->base.lock, flags); for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) - engm |= 1 << nve0_fifo_engidx(priv, engn); + engm |= 1 << gk104_fifo_engidx(priv, engn); nv_mask(priv, 0x002630, engm, engm); for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { - if ((engine = (void *)nouveau_engine(priv, engn))) { + if ((engine = (void *)nvkm_engine(priv, engn))) { nv_ofuncs(engine)->fini(engine, false); WARN_ON(nv_ofuncs(engine)->init(engine)); } - nve0_fifo_runlist_update(priv, nve0_fifo_engidx(priv, engn)); + gk104_fifo_runlist_update(priv, gk104_fifo_engidx(priv, engn)); } nv_wr32(priv, 0x00262c, engm); @@ -468,8 +460,8 @@ nve0_fifo_recover_work(struct work_struct *work) } static void -nve0_fifo_recover(struct nve0_fifo_priv *priv, struct nouveau_engine *engine, - struct nve0_fifo_chan *chan) +gk104_fifo_recover(struct gk104_fifo_priv *priv, struct nvkm_engine *engine, + struct gk104_fifo_chan *chan) { u32 chid = chan->base.chid; unsigned long flags; @@ -487,10 +479,10 @@ nve0_fifo_recover(struct nve0_fifo_priv *priv, struct nouveau_engine *engine, } static int -nve0_fifo_swmthd(struct nve0_fifo_priv *priv, u32 chid, u32 mthd, u32 data) +gk104_fifo_swmthd(struct gk104_fifo_priv *priv, u32 chid, u32 mthd, u32 data) { - struct nve0_fifo_chan *chan = NULL; - struct nouveau_handle *bind; + struct gk104_fifo_chan *chan = NULL; + struct nvkm_handle *bind; unsigned long flags; int ret = -EINVAL; @@ -500,11 +492,11 @@ nve0_fifo_swmthd(struct nve0_fifo_priv *priv, u32 chid, u32 mthd, u32 data) if (unlikely(!chan)) goto out; - bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e); + bind = nvkm_namedb_get_class(nv_namedb(chan), 0x906e); if (likely(bind)) { if (!mthd || !nv_call(bind->object, mthd, data)) ret = 0; - nouveau_namedb_put(bind); + nvkm_namedb_put(bind); } out: @@ -512,8 +504,8 @@ out: return ret; } -static const struct nouveau_enum -nve0_fifo_bind_reason[] = { +static const struct nvkm_enum +gk104_fifo_bind_reason[] = { { 0x01, "BIND_NOT_UNBOUND" }, { 0x02, "SNOOP_WITHOUT_BAR1" }, { 0x03, "UNBIND_WHILE_RUNNING" }, @@ -524,31 +516,31 @@ nve0_fifo_bind_reason[] = { }; static void -nve0_fifo_intr_bind(struct nve0_fifo_priv *priv) +gk104_fifo_intr_bind(struct gk104_fifo_priv *priv) { u32 intr = nv_rd32(priv, 0x00252c); u32 code = intr & 0x000000ff; - const struct nouveau_enum *en; + const struct nvkm_enum *en; char enunk[6] = ""; - en = nouveau_enum_find(nve0_fifo_bind_reason, code); + en = nvkm_enum_find(gk104_fifo_bind_reason, code); if (!en) snprintf(enunk, sizeof(enunk), "UNK%02x", code); nv_error(priv, "BIND_ERROR [ %s ]\n", en ? en->name : enunk); } -static const struct nouveau_enum -nve0_fifo_sched_reason[] = { +static const struct nvkm_enum +gk104_fifo_sched_reason[] = { { 0x0a, "CTXSW_TIMEOUT" }, {} }; static void -nve0_fifo_intr_sched_ctxsw(struct nve0_fifo_priv *priv) +gk104_fifo_intr_sched_ctxsw(struct gk104_fifo_priv *priv) { - struct nouveau_engine *engine; - struct nve0_fifo_chan *chan; + struct nvkm_engine *engine; + struct gk104_fifo_chan *chan; u32 engn; for (engn = 0; engn < ARRAY_SIZE(fifo_engine); engn++) { @@ -565,22 +557,22 @@ nve0_fifo_intr_sched_ctxsw(struct nve0_fifo_priv *priv) if (busy && chsw) { if (!(chan = (void *)priv->base.channel[chid])) continue; - if (!(engine = nve0_fifo_engine(priv, engn))) + if (!(engine = gk104_fifo_engine(priv, engn))) continue; - nve0_fifo_recover(priv, engine, chan); + gk104_fifo_recover(priv, engine, chan); } } } static void -nve0_fifo_intr_sched(struct nve0_fifo_priv *priv) +gk104_fifo_intr_sched(struct gk104_fifo_priv *priv) { u32 intr = nv_rd32(priv, 0x00254c); u32 code = intr & 0x000000ff; - const struct nouveau_enum *en; + const struct nvkm_enum *en; char enunk[6] = ""; - en = nouveau_enum_find(nve0_fifo_sched_reason, code); + en = nvkm_enum_find(gk104_fifo_sched_reason, code); if (!en) snprintf(enunk, sizeof(enunk), "UNK%02x", code); @@ -588,7 +580,7 @@ nve0_fifo_intr_sched(struct nve0_fifo_priv *priv) switch (code) { case 0x0a: - nve0_fifo_intr_sched_ctxsw(priv); + gk104_fifo_intr_sched_ctxsw(priv); break; default: break; @@ -596,7 +588,7 @@ nve0_fifo_intr_sched(struct nve0_fifo_priv *priv) } static void -nve0_fifo_intr_chsw(struct nve0_fifo_priv *priv) +gk104_fifo_intr_chsw(struct gk104_fifo_priv *priv) { u32 stat = nv_rd32(priv, 0x00256c); nv_error(priv, "CHSW_ERROR 0x%08x\n", stat); @@ -604,14 +596,14 @@ nve0_fifo_intr_chsw(struct nve0_fifo_priv *priv) } static void -nve0_fifo_intr_dropped_fault(struct nve0_fifo_priv *priv) +gk104_fifo_intr_dropped_fault(struct gk104_fifo_priv *priv) { u32 stat = nv_rd32(priv, 0x00259c); nv_error(priv, "DROPPED_MMU_FAULT 0x%08x\n", stat); } -static const struct nouveau_enum -nve0_fifo_fault_engine[] = { +static const struct nvkm_enum +gk104_fifo_fault_engine[] = { { 0x00, "GR", NULL, NVDEV_ENGINE_GR }, { 0x03, "IFB", NULL, NVDEV_ENGINE_IFB }, { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, @@ -631,8 +623,8 @@ nve0_fifo_fault_engine[] = { {} }; -static const struct nouveau_enum -nve0_fifo_fault_reason[] = { +static const struct nvkm_enum +gk104_fifo_fault_reason[] = { { 0x00, "PDE" }, { 0x01, "PDE_SIZE" }, { 0x02, "PTE" }, @@ -652,8 +644,8 @@ nve0_fifo_fault_reason[] = { {} }; -static const struct nouveau_enum -nve0_fifo_fault_hubclient[] = { +static const struct nvkm_enum +gk104_fifo_fault_hubclient[] = { { 0x00, "VIP" }, { 0x01, "CE0" }, { 0x02, "CE1" }, @@ -689,8 +681,8 @@ nve0_fifo_fault_hubclient[] = { {} }; -static const struct nouveau_enum -nve0_fifo_fault_gpcclient[] = { +static const struct nvkm_enum +gk104_fifo_fault_gpcclient[] = { { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" }, { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" }, { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" }, @@ -716,7 +708,7 @@ nve0_fifo_fault_gpcclient[] = { }; static void -nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) +gk104_fifo_intr_fault(struct gk104_fifo_priv *priv, int unit) { u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10)); u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10)); @@ -727,19 +719,19 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) u32 write = (stat & 0x00000080); u32 hub = (stat & 0x00000040); u32 reason = (stat & 0x0000000f); - struct nouveau_object *engctx = NULL, *object; - struct nouveau_engine *engine = NULL; - const struct nouveau_enum *er, *eu, *ec; + struct nvkm_object *engctx = NULL, *object; + struct nvkm_engine *engine = NULL; + const struct nvkm_enum *er, *eu, *ec; char erunk[6] = ""; char euunk[6] = ""; char ecunk[6] = ""; char gpcid[3] = ""; - er = nouveau_enum_find(nve0_fifo_fault_reason, reason); + er = nvkm_enum_find(gk104_fifo_fault_reason, reason); if (!er) snprintf(erunk, sizeof(erunk), "UNK%02X", reason); - eu = nouveau_enum_find(nve0_fifo_fault_engine, unit); + eu = nvkm_enum_find(gk104_fifo_fault_engine, unit); if (eu) { switch (eu->data2) { case NVDEV_SUBDEV_BAR: @@ -752,9 +744,9 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) nv_mask(priv, 0x001718, 0x00000000, 0x00000000); break; default: - engine = nouveau_engine(priv, eu->data2); + engine = nvkm_engine(priv, eu->data2); if (engine) - engctx = nouveau_engctx_get(engine, inst); + engctx = nvkm_engctx_get(engine, inst); break; } } else { @@ -762,9 +754,9 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) } if (hub) { - ec = nouveau_enum_find(nve0_fifo_fault_hubclient, client); + ec = nvkm_enum_find(gk104_fifo_fault_hubclient, client); } else { - ec = nouveau_enum_find(nve0_fifo_fault_gpcclient, client); + ec = nvkm_enum_find(gk104_fifo_fault_gpcclient, client); snprintf(gpcid, sizeof(gpcid), "%d", gpc); } @@ -776,22 +768,22 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) (u64)vahi << 32 | valo, er ? er->name : erunk, eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/", ec ? ec->name : ecunk, (u64)inst << 12, - nouveau_client_name(engctx)); + nvkm_client_name(engctx)); object = engctx; while (object) { switch (nv_mclass(object)) { case KEPLER_CHANNEL_GPFIFO_A: - nve0_fifo_recover(priv, engine, (void *)object); + gk104_fifo_recover(priv, engine, (void *)object); break; } object = object->parent; } - nouveau_engctx_put(engctx); + nvkm_engctx_put(engctx); } -static const struct nouveau_bitfield nve0_fifo_pbdma_intr_0[] = { +static const struct nvkm_bitfield gk104_fifo_pbdma_intr_0[] = { { 0x00000001, "MEMREQ" }, { 0x00000002, "MEMACK_TIMEOUT" }, { 0x00000004, "MEMACK_EXTRA" }, @@ -826,7 +818,7 @@ static const struct nouveau_bitfield nve0_fifo_pbdma_intr_0[] = { }; static void -nve0_fifo_intr_pbdma_0(struct nve0_fifo_priv *priv, int unit) +gk104_fifo_intr_pbdma_0(struct gk104_fifo_priv *priv, int unit) { u32 mask = nv_rd32(priv, 0x04010c + (unit * 0x2000)); u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)) & mask; @@ -838,26 +830,26 @@ nve0_fifo_intr_pbdma_0(struct nve0_fifo_priv *priv, int unit) u32 show = stat; if (stat & 0x00800000) { - if (!nve0_fifo_swmthd(priv, chid, mthd, data)) + if (!gk104_fifo_swmthd(priv, chid, mthd, data)) show &= ~0x00800000; nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008); } if (show) { nv_error(priv, "PBDMA%d:", unit); - nouveau_bitfield_print(nve0_fifo_pbdma_intr_0, show); + nvkm_bitfield_print(gk104_fifo_pbdma_intr_0, show); pr_cont("\n"); nv_error(priv, "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", unit, chid, - nouveau_client_name_for_fifo_chid(&priv->base, chid), + nvkm_client_name_for_fifo_chid(&priv->base, chid), subc, mthd, data); } nv_wr32(priv, 0x040108 + (unit * 0x2000), stat); } -static const struct nouveau_bitfield nve0_fifo_pbdma_intr_1[] = { +static const struct nvkm_bitfield gk104_fifo_pbdma_intr_1[] = { { 0x00000001, "HCE_RE_ILLEGAL_OP" }, { 0x00000002, "HCE_RE_ALIGNB" }, { 0x00000004, "HCE_PRIV" }, @@ -867,7 +859,7 @@ static const struct nouveau_bitfield nve0_fifo_pbdma_intr_1[] = { }; static void -nve0_fifo_intr_pbdma_1(struct nve0_fifo_priv *priv, int unit) +gk104_fifo_intr_pbdma_1(struct gk104_fifo_priv *priv, int unit) { u32 mask = nv_rd32(priv, 0x04014c + (unit * 0x2000)); u32 stat = nv_rd32(priv, 0x040148 + (unit * 0x2000)) & mask; @@ -875,7 +867,7 @@ nve0_fifo_intr_pbdma_1(struct nve0_fifo_priv *priv, int unit) if (stat) { nv_error(priv, "PBDMA%d:", unit); - nouveau_bitfield_print(nve0_fifo_pbdma_intr_1, stat); + nvkm_bitfield_print(gk104_fifo_pbdma_intr_1, stat); pr_cont("\n"); nv_error(priv, "PBDMA%d: ch %d %08x %08x\n", unit, chid, nv_rd32(priv, 0x040150 + (unit * 0x2000)), @@ -886,7 +878,7 @@ nve0_fifo_intr_pbdma_1(struct nve0_fifo_priv *priv, int unit) } static void -nve0_fifo_intr_runlist(struct nve0_fifo_priv *priv) +gk104_fifo_intr_runlist(struct gk104_fifo_priv *priv) { u32 mask = nv_rd32(priv, 0x002a00); while (mask) { @@ -898,20 +890,20 @@ nve0_fifo_intr_runlist(struct nve0_fifo_priv *priv) } static void -nve0_fifo_intr_engine(struct nve0_fifo_priv *priv) +gk104_fifo_intr_engine(struct gk104_fifo_priv *priv) { - nouveau_fifo_uevent(&priv->base); + nvkm_fifo_uevent(&priv->base); } static void -nve0_fifo_intr(struct nouveau_subdev *subdev) +gk104_fifo_intr(struct nvkm_subdev *subdev) { - struct nve0_fifo_priv *priv = (void *)subdev; + struct gk104_fifo_priv *priv = (void *)subdev; u32 mask = nv_rd32(priv, 0x002140); u32 stat = nv_rd32(priv, 0x002100) & mask; if (stat & 0x00000001) { - nve0_fifo_intr_bind(priv); + gk104_fifo_intr_bind(priv); nv_wr32(priv, 0x002100, 0x00000001); stat &= ~0x00000001; } @@ -923,13 +915,13 @@ nve0_fifo_intr(struct nouveau_subdev *subdev) } if (stat & 0x00000100) { - nve0_fifo_intr_sched(priv); + gk104_fifo_intr_sched(priv); nv_wr32(priv, 0x002100, 0x00000100); stat &= ~0x00000100; } if (stat & 0x00010000) { - nve0_fifo_intr_chsw(priv); + gk104_fifo_intr_chsw(priv); nv_wr32(priv, 0x002100, 0x00010000); stat &= ~0x00010000; } @@ -947,7 +939,7 @@ nve0_fifo_intr(struct nouveau_subdev *subdev) } if (stat & 0x08000000) { - nve0_fifo_intr_dropped_fault(priv); + gk104_fifo_intr_dropped_fault(priv); nv_wr32(priv, 0x002100, 0x08000000); stat &= ~0x08000000; } @@ -956,7 +948,7 @@ nve0_fifo_intr(struct nouveau_subdev *subdev) u32 mask = nv_rd32(priv, 0x00259c); while (mask) { u32 unit = __ffs(mask); - nve0_fifo_intr_fault(priv, unit); + gk104_fifo_intr_fault(priv, unit); nv_wr32(priv, 0x00259c, (1 << unit)); mask &= ~(1 << unit); } @@ -967,8 +959,8 @@ nve0_fifo_intr(struct nouveau_subdev *subdev) u32 mask = nv_rd32(priv, 0x0025a0); while (mask) { u32 unit = __ffs(mask); - nve0_fifo_intr_pbdma_0(priv, unit); - nve0_fifo_intr_pbdma_1(priv, unit); + gk104_fifo_intr_pbdma_0(priv, unit); + gk104_fifo_intr_pbdma_1(priv, unit); nv_wr32(priv, 0x0025a0, (1 << unit)); mask &= ~(1 << unit); } @@ -976,13 +968,13 @@ nve0_fifo_intr(struct nouveau_subdev *subdev) } if (stat & 0x40000000) { - nve0_fifo_intr_runlist(priv); + gk104_fifo_intr_runlist(priv); stat &= ~0x40000000; } if (stat & 0x80000000) { nv_wr32(priv, 0x002100, 0x80000000); - nve0_fifo_intr_engine(priv); + gk104_fifo_intr_engine(priv); stat &= ~0x80000000; } @@ -994,33 +986,33 @@ nve0_fifo_intr(struct nouveau_subdev *subdev) } static void -nve0_fifo_uevent_init(struct nvkm_event *event, int type, int index) +gk104_fifo_uevent_init(struct nvkm_event *event, int type, int index) { - struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); nv_mask(fifo, 0x002140, 0x80000000, 0x80000000); } static void -nve0_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +gk104_fifo_uevent_fini(struct nvkm_event *event, int type, int index) { - struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); nv_mask(fifo, 0x002140, 0x80000000, 0x00000000); } static const struct nvkm_event_func -nve0_fifo_uevent_func = { - .ctor = nouveau_fifo_uevent_ctor, - .init = nve0_fifo_uevent_init, - .fini = nve0_fifo_uevent_fini, +gk104_fifo_uevent_func = { + .ctor = nvkm_fifo_uevent_ctor, + .init = gk104_fifo_uevent_init, + .fini = gk104_fifo_uevent_fini, }; int -nve0_fifo_fini(struct nouveau_object *object, bool suspend) +gk104_fifo_fini(struct nvkm_object *object, bool suspend) { - struct nve0_fifo_priv *priv = (void *)object; + struct gk104_fifo_priv *priv = (void *)object; int ret; - ret = nouveau_fifo_fini(&priv->base, suspend); + ret = nvkm_fifo_fini(&priv->base, suspend); if (ret) return ret; @@ -1030,12 +1022,12 @@ nve0_fifo_fini(struct nouveau_object *object, bool suspend) } int -nve0_fifo_init(struct nouveau_object *object) +gk104_fifo_init(struct nvkm_object *object) { - struct nve0_fifo_priv *priv = (void *)object; + struct gk104_fifo_priv *priv = (void *)object; int ret, i; - ret = nouveau_fifo_init(&priv->base); + ret = nvkm_fifo_init(&priv->base); if (ret) return ret; @@ -1065,82 +1057,82 @@ nve0_fifo_init(struct nouveau_object *object) } void -nve0_fifo_dtor(struct nouveau_object *object) +gk104_fifo_dtor(struct nvkm_object *object) { - struct nve0_fifo_priv *priv = (void *)object; + struct gk104_fifo_priv *priv = (void *)object; int i; - nouveau_gpuobj_unmap(&priv->user.bar); - nouveau_gpuobj_ref(NULL, &priv->user.mem); + nvkm_gpuobj_unmap(&priv->user.bar); + nvkm_gpuobj_ref(NULL, &priv->user.mem); for (i = 0; i < FIFO_ENGINE_NR; i++) { - nouveau_gpuobj_ref(NULL, &priv->engine[i].runlist[1]); - nouveau_gpuobj_ref(NULL, &priv->engine[i].runlist[0]); + nvkm_gpuobj_ref(NULL, &priv->engine[i].runlist[1]); + nvkm_gpuobj_ref(NULL, &priv->engine[i].runlist[0]); } - nouveau_fifo_destroy(&priv->base); + nvkm_fifo_destroy(&priv->base); } int -nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk104_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nve0_fifo_impl *impl = (void *)oclass; - struct nve0_fifo_priv *priv; + struct gk104_fifo_impl *impl = (void *)oclass; + struct gk104_fifo_priv *priv; int ret, i; - ret = nouveau_fifo_create(parent, engine, oclass, 0, - impl->channels - 1, &priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, + impl->channels - 1, &priv); *pobject = nv_object(priv); if (ret) return ret; - INIT_WORK(&priv->fault, nve0_fifo_recover_work); + INIT_WORK(&priv->fault, gk104_fifo_recover_work); for (i = 0; i < FIFO_ENGINE_NR; i++) { - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, - 0, &priv->engine[i].runlist[0]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, + 0, &priv->engine[i].runlist[0]); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, - 0, &priv->engine[i].runlist[1]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, + 0, &priv->engine[i].runlist[1]); if (ret) return ret; init_waitqueue_head(&priv->engine[i].wait); } - ret = nouveau_gpuobj_new(nv_object(priv), NULL, impl->channels * 0x200, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, impl->channels * 0x200, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem); if (ret) return ret; - ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, - &priv->user.bar); + ret = nvkm_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, + &priv->user.bar); if (ret) return ret; - ret = nvkm_event_init(&nve0_fifo_uevent_func, 1, 1, &priv->base.uevent); + ret = nvkm_event_init(&gk104_fifo_uevent_func, 1, 1, &priv->base.uevent); if (ret) return ret; nv_subdev(priv)->unit = 0x00000100; - nv_subdev(priv)->intr = nve0_fifo_intr; - nv_engine(priv)->cclass = &nve0_fifo_cclass; - nv_engine(priv)->sclass = nve0_fifo_sclass; + nv_subdev(priv)->intr = gk104_fifo_intr; + nv_engine(priv)->cclass = &gk104_fifo_cclass; + nv_engine(priv)->sclass = gk104_fifo_sclass; return 0; } -struct nouveau_oclass * -nve0_fifo_oclass = &(struct nve0_fifo_impl) { +struct nvkm_oclass * +gk104_fifo_oclass = &(struct gk104_fifo_impl) { .base.handle = NV_ENGINE(FIFO, 0xe0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_fifo_ctor, - .dtor = nve0_fifo_dtor, - .init = nve0_fifo_init, - .fini = nve0_fifo_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_fifo_ctor, + .dtor = gk104_fifo_dtor, + .init = gk104_fifo_init, + .fini = gk104_fifo_fini, }, .channels = 4096, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h new file mode 100644 index 000000000000..3046e00ed6ba --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h @@ -0,0 +1,16 @@ +#ifndef __NVKM_FIFO_NVE0_H__ +#define __NVKM_FIFO_NVE0_H__ +#include <engine/fifo.h> + +int gk104_fifo_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void gk104_fifo_dtor(struct nvkm_object *); +int gk104_fifo_init(struct nvkm_object *); +int gk104_fifo_fini(struct nvkm_object *, bool); + +struct gk104_fifo_impl { + struct nvkm_oclass base; + u32 channels; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c index 09362a51ba57..927092217a06 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c @@ -21,17 +21,16 @@ * * Authors: Ben Skeggs */ +#include "gk104.h" -#include "nve0.h" - -struct nouveau_oclass * -nv108_fifo_oclass = &(struct nve0_fifo_impl) { +struct nvkm_oclass * +gk208_fifo_oclass = &(struct gk104_fifo_impl) { .base.handle = NV_ENGINE(FIFO, 0x08), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_fifo_ctor, - .dtor = nve0_fifo_dtor, - .init = nve0_fifo_init, - .fini = _nouveau_fifo_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_fifo_ctor, + .dtor = gk104_fifo_dtor, + .init = gk104_fifo_init, + .fini = _nvkm_fifo_fini, }, .channels = 1024, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c index 327456eae963..b30dc87a1357 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c @@ -19,17 +19,16 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ +#include "gk104.h" -#include "nve0.h" - -struct nouveau_oclass * -gk20a_fifo_oclass = &(struct nve0_fifo_impl) { +struct nvkm_oclass * +gk20a_fifo_oclass = &(struct gk104_fifo_impl) { .base.handle = NV_ENGINE(FIFO, 0xea), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_fifo_ctor, - .dtor = nve0_fifo_dtor, - .init = nve0_fifo_init, - .fini = nve0_fifo_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_fifo_ctor, + .dtor = gk104_fifo_dtor, + .init = gk104_fifo_init, + .fini = gk104_fifo_fini, }, .channels = 128, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c index 1b384bd5994e..b038b6eb51db 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c @@ -21,25 +21,18 @@ * * Authors: Ben Skeggs */ +#include "nv04.h" #include <core/client.h> #include <core/device.h> -#include <nvif/unpack.h> -#include <nvif/class.h> #include <core/engctx.h> -#include <core/namedb.h> #include <core/handle.h> #include <core/ramht.h> -#include <core/event.h> - -#include <subdev/instmem.h> #include <subdev/instmem/nv04.h> #include <subdev/timer.h> -#include <subdev/fb.h> -#include <engine/fifo.h> - -#include "nv04.h" +#include <nvif/class.h> +#include <nvif/unpack.h> static struct ramfc_desc nv04_ramfc[] = { @@ -59,8 +52,8 @@ nv04_ramfc[] = { ******************************************************************************/ int -nv04_fifo_object_attach(struct nouveau_object *parent, - struct nouveau_object *object, u32 handle) +nv04_fifo_object_attach(struct nvkm_object *parent, + struct nvkm_object *object, u32 handle) { struct nv04_fifo_priv *priv = (void *)parent->engine; struct nv04_fifo_chan *chan = (void *)parent; @@ -91,33 +84,33 @@ nv04_fifo_object_attach(struct nouveau_object *parent, context |= chid << 24; mutex_lock(&nv_subdev(priv)->mutex); - ret = nouveau_ramht_insert(priv->ramht, chid, handle, context); + ret = nvkm_ramht_insert(priv->ramht, chid, handle, context); mutex_unlock(&nv_subdev(priv)->mutex); return ret; } void -nv04_fifo_object_detach(struct nouveau_object *parent, int cookie) +nv04_fifo_object_detach(struct nvkm_object *parent, int cookie) { struct nv04_fifo_priv *priv = (void *)parent->engine; mutex_lock(&nv_subdev(priv)->mutex); - nouveau_ramht_remove(priv->ramht, cookie); + nvkm_ramht_remove(priv->ramht, cookie); mutex_unlock(&nv_subdev(priv)->mutex); } int -nv04_fifo_context_attach(struct nouveau_object *parent, - struct nouveau_object *object) +nv04_fifo_context_attach(struct nvkm_object *parent, + struct nvkm_object *object) { - nv_engctx(object)->addr = nouveau_fifo_chan(parent)->chid; + nv_engctx(object)->addr = nvkm_fifo_chan(parent)->chid; return 0; } static int -nv04_fifo_chan_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_fifo_chan_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv03_channel_dma_v0 v0; @@ -134,11 +127,11 @@ nv04_fifo_chan_ctor(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, - 0x10000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR), &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, + 0x10000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR), &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -164,7 +157,7 @@ nv04_fifo_chan_ctor(struct nouveau_object *parent, } void -nv04_fifo_chan_dtor(struct nouveau_object *object) +nv04_fifo_chan_dtor(struct nvkm_object *object) { struct nv04_fifo_priv *priv = (void *)object->engine; struct nv04_fifo_chan *chan = (void *)object; @@ -174,11 +167,11 @@ nv04_fifo_chan_dtor(struct nouveau_object *object) nv_wo32(priv->ramfc, chan->ramfc + c->ctxp, 0x00000000); } while ((++c)->bits); - nouveau_fifo_channel_destroy(&chan->base); + nvkm_fifo_channel_destroy(&chan->base); } int -nv04_fifo_chan_init(struct nouveau_object *object) +nv04_fifo_chan_init(struct nvkm_object *object) { struct nv04_fifo_priv *priv = (void *)object->engine; struct nv04_fifo_chan *chan = (void *)object; @@ -186,7 +179,7 @@ nv04_fifo_chan_init(struct nouveau_object *object) unsigned long flags; int ret; - ret = nouveau_fifo_channel_init(&chan->base); + ret = nvkm_fifo_channel_init(&chan->base); if (ret) return ret; @@ -197,11 +190,11 @@ nv04_fifo_chan_init(struct nouveau_object *object) } int -nv04_fifo_chan_fini(struct nouveau_object *object, bool suspend) +nv04_fifo_chan_fini(struct nvkm_object *object, bool suspend) { struct nv04_fifo_priv *priv = (void *)object->engine; struct nv04_fifo_chan *chan = (void *)object; - struct nouveau_gpuobj *fctx = priv->ramfc; + struct nvkm_gpuobj *fctx = priv->ramfc; struct ramfc_desc *c; unsigned long flags; u32 data = chan->ramfc; @@ -244,22 +237,22 @@ nv04_fifo_chan_fini(struct nouveau_object *object, bool suspend) nv_wr32(priv, NV03_PFIFO_CACHES, 1); spin_unlock_irqrestore(&priv->base.lock, flags); - return nouveau_fifo_channel_fini(&chan->base, suspend); + return nvkm_fifo_channel_fini(&chan->base, suspend); } -static struct nouveau_ofuncs +static struct nvkm_ofuncs nv04_fifo_ofuncs = { .ctor = nv04_fifo_chan_ctor, .dtor = nv04_fifo_chan_dtor, .init = nv04_fifo_chan_init, .fini = nv04_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_oclass +static struct nvkm_oclass nv04_fifo_sclass[] = { { NV03_CHANNEL_DMA, &nv04_fifo_ofuncs }, {} @@ -270,16 +263,16 @@ nv04_fifo_sclass[] = { ******************************************************************************/ int -nv04_fifo_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_fifo_context_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_fifo_base *base; int ret; - ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000, - 0x1000, NVOBJ_FLAG_HEAP, &base); + ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, + 0x1000, NVOBJ_FLAG_HEAP, &base); *pobject = nv_object(base); if (ret) return ret; @@ -287,16 +280,16 @@ nv04_fifo_context_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_oclass +static struct nvkm_oclass nv04_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fifo_context_ctor, - .dtor = _nouveau_fifo_context_dtor, - .init = _nouveau_fifo_context_init, - .fini = _nouveau_fifo_context_fini, - .rd32 = _nouveau_fifo_context_rd32, - .wr32 = _nouveau_fifo_context_wr32, + .dtor = _nvkm_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, }, }; @@ -305,7 +298,7 @@ nv04_fifo_cclass = { ******************************************************************************/ void -nv04_fifo_pause(struct nouveau_fifo *pfifo, unsigned long *pflags) +nv04_fifo_pause(struct nvkm_fifo *pfifo, unsigned long *pflags) __acquires(priv->base.lock) { struct nv04_fifo_priv *priv = (void *)pfifo; @@ -338,7 +331,7 @@ __acquires(priv->base.lock) } void -nv04_fifo_start(struct nouveau_fifo *pfifo, unsigned long *pflags) +nv04_fifo_start(struct nvkm_fifo *pfifo, unsigned long *pflags) __releases(priv->base.lock) { struct nv04_fifo_priv *priv = (void *)pfifo; @@ -364,7 +357,7 @@ static bool nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data) { struct nv04_fifo_chan *chan = NULL; - struct nouveau_handle *bind; + struct nvkm_handle *bind; const int subc = (addr >> 13) & 0x7; const int mthd = addr & 0x1ffc; bool handled = false; @@ -379,7 +372,7 @@ nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data) switch (mthd) { case 0x0000: - bind = nouveau_namedb_get(nv_namedb(chan), data); + bind = nvkm_namedb_get(nv_namedb(chan), data); if (unlikely(!bind)) break; @@ -391,18 +384,18 @@ nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data) nv_mask(priv, NV04_PFIFO_CACHE1_ENGINE, engine, 0); } - nouveau_namedb_put(bind); + nvkm_namedb_put(bind); break; default: engine = nv_rd32(priv, NV04_PFIFO_CACHE1_ENGINE); if (unlikely(((engine >> (subc * 4)) & 0xf) != 0)) break; - bind = nouveau_namedb_get(nv_namedb(chan), chan->subc[subc]); + bind = nvkm_namedb_get(nv_namedb(chan), chan->subc[subc]); if (likely(bind)) { if (!nv_call(bind->object, mthd, data)) handled = true; - nouveau_namedb_put(bind); + nvkm_namedb_put(bind); } break; } @@ -413,8 +406,8 @@ out: } static void -nv04_fifo_cache_error(struct nouveau_device *device, - struct nv04_fifo_priv *priv, u32 chid, u32 get) +nv04_fifo_cache_error(struct nvkm_device *device, + struct nv04_fifo_priv *priv, u32 chid, u32 get) { u32 mthd, data; int ptr; @@ -436,7 +429,7 @@ nv04_fifo_cache_error(struct nouveau_device *device, if (!nv04_fifo_swmthd(priv, chid, mthd, data)) { const char *client_name = - nouveau_client_name_for_fifo_chid(&priv->base, chid); + nvkm_client_name_for_fifo_chid(&priv->base, chid); nv_error(priv, "CACHE_ERROR - ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", chid, client_name, (mthd >> 13) & 7, mthd & 0x1ffc, @@ -459,8 +452,8 @@ nv04_fifo_cache_error(struct nouveau_device *device, } static void -nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv, - u32 chid) +nv04_fifo_dma_pusher(struct nvkm_device *device, + struct nv04_fifo_priv *priv, u32 chid) { const char *client_name; u32 dma_get = nv_rd32(priv, 0x003244); @@ -468,7 +461,7 @@ nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv, u32 push = nv_rd32(priv, 0x003220); u32 state = nv_rd32(priv, 0x003228); - client_name = nouveau_client_name_for_fifo_chid(&priv->base, chid); + client_name = nvkm_client_name_for_fifo_chid(&priv->base, chid); if (device->card_type == NV_50) { u32 ho_get = nv_rd32(priv, 0x003328); @@ -505,9 +498,9 @@ nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv, } void -nv04_fifo_intr(struct nouveau_subdev *subdev) +nv04_fifo_intr(struct nvkm_subdev *subdev) { - struct nouveau_device *device = nv_device(subdev); + struct nvkm_device *device = nv_device(subdev); struct nv04_fifo_priv *priv = (void *)subdev; uint32_t status, reassign; int cnt = 0; @@ -553,7 +546,7 @@ nv04_fifo_intr(struct nouveau_subdev *subdev) if (status & 0x40000000) { nv_wr32(priv, 0x002100, 0x40000000); - nouveau_fifo_uevent(&priv->base); + nvkm_fifo_uevent(&priv->base); status &= ~0x40000000; } } @@ -578,22 +571,22 @@ nv04_fifo_intr(struct nouveau_subdev *subdev) } static int -nv04_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_instmem_priv *imem = nv04_instmem(parent); struct nv04_fifo_priv *priv; int ret; - ret = nouveau_fifo_create(parent, engine, oclass, 0, 15, &priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, 15, &priv); *pobject = nv_object(priv); if (ret) return ret; - nouveau_ramht_ref(imem->ramht, &priv->ramht); - nouveau_gpuobj_ref(imem->ramro, &priv->ramro); - nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); + nvkm_ramht_ref(imem->ramht, &priv->ramht); + nvkm_gpuobj_ref(imem->ramro, &priv->ramro); + nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); nv_subdev(priv)->unit = 0x00000100; nv_subdev(priv)->intr = nv04_fifo_intr; @@ -606,22 +599,22 @@ nv04_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } void -nv04_fifo_dtor(struct nouveau_object *object) +nv04_fifo_dtor(struct nvkm_object *object) { struct nv04_fifo_priv *priv = (void *)object; - nouveau_gpuobj_ref(NULL, &priv->ramfc); - nouveau_gpuobj_ref(NULL, &priv->ramro); - nouveau_ramht_ref(NULL, &priv->ramht); - nouveau_fifo_destroy(&priv->base); + nvkm_gpuobj_ref(NULL, &priv->ramfc); + nvkm_gpuobj_ref(NULL, &priv->ramro); + nvkm_ramht_ref(NULL, &priv->ramht); + nvkm_fifo_destroy(&priv->base); } int -nv04_fifo_init(struct nouveau_object *object) +nv04_fifo_init(struct nvkm_object *object) { struct nv04_fifo_priv *priv = (void *)object; int ret; - ret = nouveau_fifo_init(&priv->base); + ret = nvkm_fifo_init(&priv->base); if (ret) return ret; @@ -645,13 +638,13 @@ nv04_fifo_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * -nv04_fifo_oclass = &(struct nouveau_oclass) { +struct nvkm_oclass * +nv04_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fifo_ctor, .dtor = nv04_fifo_dtor, .init = nv04_fifo_init, - .fini = _nouveau_fifo_fini, + .fini = _nvkm_fifo_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h index 496a4b4fdfaf..e0e0c47cb4ca 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h @@ -1,6 +1,5 @@ #ifndef __NV04_FIFO_H__ #define __NV04_FIFO_H__ - #include <engine/fifo.h> #define NV04_PFIFO_DELAY_0 0x00002040 @@ -141,38 +140,36 @@ struct ramfc_desc { }; struct nv04_fifo_priv { - struct nouveau_fifo base; + struct nvkm_fifo base; struct ramfc_desc *ramfc_desc; - struct nouveau_ramht *ramht; - struct nouveau_gpuobj *ramro; - struct nouveau_gpuobj *ramfc; + struct nvkm_ramht *ramht; + struct nvkm_gpuobj *ramro; + struct nvkm_gpuobj *ramfc; }; struct nv04_fifo_base { - struct nouveau_fifo_base base; + struct nvkm_fifo_base base; }; struct nv04_fifo_chan { - struct nouveau_fifo_chan base; + struct nvkm_fifo_chan base; u32 subc[8]; u32 ramfc; }; -int nv04_fifo_object_attach(struct nouveau_object *, - struct nouveau_object *, u32); -void nv04_fifo_object_detach(struct nouveau_object *, int); - -void nv04_fifo_chan_dtor(struct nouveau_object *); -int nv04_fifo_chan_init(struct nouveau_object *); -int nv04_fifo_chan_fini(struct nouveau_object *, bool suspend); +int nv04_fifo_object_attach(struct nvkm_object *, struct nvkm_object *, u32); +void nv04_fifo_object_detach(struct nvkm_object *, int); -int nv04_fifo_context_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); +void nv04_fifo_chan_dtor(struct nvkm_object *); +int nv04_fifo_chan_init(struct nvkm_object *); +int nv04_fifo_chan_fini(struct nvkm_object *, bool suspend); -void nv04_fifo_dtor(struct nouveau_object *); -int nv04_fifo_init(struct nouveau_object *); -void nv04_fifo_pause(struct nouveau_fifo *, unsigned long *); -void nv04_fifo_start(struct nouveau_fifo *, unsigned long *); +int nv04_fifo_context_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void nv04_fifo_dtor(struct nvkm_object *); +int nv04_fifo_init(struct nvkm_object *); +void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *); +void nv04_fifo_start(struct nvkm_fifo *, unsigned long *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c index 2a32add51c81..48ce4af6f543 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c @@ -21,20 +21,15 @@ * * Authors: Ben Skeggs */ +#include "nv04.h" #include <core/client.h> -#include <nvif/unpack.h> -#include <nvif/class.h> #include <core/engctx.h> #include <core/ramht.h> - -#include <subdev/instmem.h> #include <subdev/instmem/nv04.h> -#include <subdev/fb.h> -#include <engine/fifo.h> - -#include "nv04.h" +#include <nvif/class.h> +#include <nvif/unpack.h> static struct ramfc_desc nv10_ramfc[] = { @@ -55,10 +50,10 @@ nv10_ramfc[] = { ******************************************************************************/ static int -nv10_fifo_chan_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv10_fifo_chan_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv03_channel_dma_v0 v0; @@ -75,11 +70,11 @@ nv10_fifo_chan_ctor(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, - 0x10000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR), &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, + 0x10000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR), &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -104,19 +99,19 @@ nv10_fifo_chan_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_ofuncs +static struct nvkm_ofuncs nv10_fifo_ofuncs = { .ctor = nv10_fifo_chan_ctor, .dtor = nv04_fifo_chan_dtor, .init = nv04_fifo_chan_init, .fini = nv04_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_oclass +static struct nvkm_oclass nv10_fifo_sclass[] = { { NV10_CHANNEL_DMA, &nv10_fifo_ofuncs }, {} @@ -126,16 +121,16 @@ nv10_fifo_sclass[] = { * FIFO context - basically just the instmem reserved for the channel ******************************************************************************/ -static struct nouveau_oclass +static struct nvkm_oclass nv10_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0x10), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fifo_context_ctor, - .dtor = _nouveau_fifo_context_dtor, - .init = _nouveau_fifo_context_init, - .fini = _nouveau_fifo_context_fini, - .rd32 = _nouveau_fifo_context_rd32, - .wr32 = _nouveau_fifo_context_wr32, + .dtor = _nvkm_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, }, }; @@ -144,22 +139,22 @@ nv10_fifo_cclass = { ******************************************************************************/ static int -nv10_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv10_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_instmem_priv *imem = nv04_instmem(parent); struct nv04_fifo_priv *priv; int ret; - ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); *pobject = nv_object(priv); if (ret) return ret; - nouveau_ramht_ref(imem->ramht, &priv->ramht); - nouveau_gpuobj_ref(imem->ramro, &priv->ramro); - nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); + nvkm_ramht_ref(imem->ramht, &priv->ramht); + nvkm_gpuobj_ref(imem->ramro, &priv->ramro); + nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); nv_subdev(priv)->unit = 0x00000100; nv_subdev(priv)->intr = nv04_fifo_intr; @@ -171,13 +166,13 @@ nv10_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass * -nv10_fifo_oclass = &(struct nouveau_oclass) { +struct nvkm_oclass * +nv10_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0x10), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv10_fifo_ctor, .dtor = nv04_fifo_dtor, .init = nv04_fifo_init, - .fini = _nouveau_fifo_fini, + .fini = _nvkm_fifo_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c index 01fbb11af00d..4a20a6fd3887 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c @@ -21,20 +21,15 @@ * * Authors: Ben Skeggs */ +#include "nv04.h" #include <core/client.h> -#include <nvif/unpack.h> -#include <nvif/class.h> #include <core/engctx.h> #include <core/ramht.h> - -#include <subdev/instmem.h> #include <subdev/instmem/nv04.h> -#include <subdev/fb.h> -#include <engine/fifo.h> - -#include "nv04.h" +#include <nvif/class.h> +#include <nvif/unpack.h> static struct ramfc_desc nv17_ramfc[] = { @@ -60,10 +55,10 @@ nv17_ramfc[] = { ******************************************************************************/ static int -nv17_fifo_chan_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv17_fifo_chan_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv03_channel_dma_v0 v0; @@ -80,13 +75,13 @@ nv17_fifo_chan_ctor(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, - 0x10000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), /* NV31- */ - &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, + 0x10000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG), /* NV31- */ + &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -111,19 +106,19 @@ nv17_fifo_chan_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_ofuncs +static struct nvkm_ofuncs nv17_fifo_ofuncs = { .ctor = nv17_fifo_chan_ctor, .dtor = nv04_fifo_chan_dtor, .init = nv04_fifo_chan_init, .fini = nv04_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_oclass +static struct nvkm_oclass nv17_fifo_sclass[] = { { NV17_CHANNEL_DMA, &nv17_fifo_ofuncs }, {} @@ -133,16 +128,16 @@ nv17_fifo_sclass[] = { * FIFO context - basically just the instmem reserved for the channel ******************************************************************************/ -static struct nouveau_oclass +static struct nvkm_oclass nv17_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0x17), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fifo_context_ctor, - .dtor = _nouveau_fifo_context_dtor, - .init = _nouveau_fifo_context_init, - .fini = _nouveau_fifo_context_fini, - .rd32 = _nouveau_fifo_context_rd32, - .wr32 = _nouveau_fifo_context_wr32, + .dtor = _nvkm_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, }, }; @@ -151,22 +146,22 @@ nv17_fifo_cclass = { ******************************************************************************/ static int -nv17_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_instmem_priv *imem = nv04_instmem(parent); struct nv04_fifo_priv *priv; int ret; - ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); *pobject = nv_object(priv); if (ret) return ret; - nouveau_ramht_ref(imem->ramht, &priv->ramht); - nouveau_gpuobj_ref(imem->ramro, &priv->ramro); - nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); + nvkm_ramht_ref(imem->ramht, &priv->ramht); + nvkm_gpuobj_ref(imem->ramro, &priv->ramro); + nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); nv_subdev(priv)->unit = 0x00000100; nv_subdev(priv)->intr = nv04_fifo_intr; @@ -179,12 +174,12 @@ nv17_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } static int -nv17_fifo_init(struct nouveau_object *object) +nv17_fifo_init(struct nvkm_object *object) { struct nv04_fifo_priv *priv = (void *)object; int ret; - ret = nouveau_fifo_init(&priv->base); + ret = nvkm_fifo_init(&priv->base); if (ret) return ret; @@ -208,13 +203,13 @@ nv17_fifo_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * -nv17_fifo_oclass = &(struct nouveau_oclass) { +struct nvkm_oclass * +nv17_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0x17), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv17_fifo_ctor, .dtor = nv04_fifo_dtor, .init = nv17_fifo_init, - .fini = _nouveau_fifo_fini, + .fini = _nvkm_fifo_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index be0293476279..5bfc96265f3b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -21,21 +21,17 @@ * * Authors: Ben Skeggs */ +#include "nv04.h" #include <core/client.h> #include <core/device.h> -#include <nvif/unpack.h> -#include <nvif/class.h> #include <core/engctx.h> #include <core/ramht.h> - -#include <subdev/instmem.h> -#include <subdev/instmem/nv04.h> #include <subdev/fb.h> +#include <subdev/instmem/nv04.h> -#include <engine/fifo.h> - -#include "nv04.h" +#include <nvif/class.h> +#include <nvif/unpack.h> static struct ramfc_desc nv40_ramfc[] = { @@ -69,8 +65,8 @@ nv40_ramfc[] = { ******************************************************************************/ static int -nv40_fifo_object_attach(struct nouveau_object *parent, - struct nouveau_object *object, u32 handle) +nv40_fifo_object_attach(struct nvkm_object *parent, + struct nvkm_object *object, u32 handle) { struct nv04_fifo_priv *priv = (void *)parent->engine; struct nv04_fifo_chan *chan = (void *)parent; @@ -100,14 +96,13 @@ nv40_fifo_object_attach(struct nouveau_object *parent, context |= chid << 23; mutex_lock(&nv_subdev(priv)->mutex); - ret = nouveau_ramht_insert(priv->ramht, chid, handle, context); + ret = nvkm_ramht_insert(priv->ramht, chid, handle, context); mutex_unlock(&nv_subdev(priv)->mutex); return ret; } static int -nv40_fifo_context_attach(struct nouveau_object *parent, - struct nouveau_object *engctx) +nv40_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *engctx) { struct nv04_fifo_priv *priv = (void *)parent->engine; struct nv04_fifo_chan *chan = (void *)parent; @@ -143,8 +138,8 @@ nv40_fifo_context_attach(struct nouveau_object *parent, } static int -nv40_fifo_context_detach(struct nouveau_object *parent, bool suspend, - struct nouveau_object *engctx) +nv40_fifo_context_detach(struct nvkm_object *parent, bool suspend, + struct nvkm_object *engctx) { struct nv04_fifo_priv *priv = (void *)parent->engine; struct nv04_fifo_chan *chan = (void *)parent; @@ -179,10 +174,9 @@ nv40_fifo_context_detach(struct nouveau_object *parent, bool suspend, } static int -nv40_fifo_chan_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv03_channel_dma_v0 v0; @@ -199,12 +193,12 @@ nv40_fifo_chan_ctor(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x1000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, + 0x1000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG), &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -231,19 +225,19 @@ nv40_fifo_chan_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_ofuncs +static struct nvkm_ofuncs nv40_fifo_ofuncs = { .ctor = nv40_fifo_chan_ctor, .dtor = nv04_fifo_chan_dtor, .init = nv04_fifo_chan_init, .fini = nv04_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_oclass +static struct nvkm_oclass nv40_fifo_sclass[] = { { NV40_CHANNEL_DMA, &nv40_fifo_ofuncs }, {} @@ -253,16 +247,16 @@ nv40_fifo_sclass[] = { * FIFO context - basically just the instmem reserved for the channel ******************************************************************************/ -static struct nouveau_oclass +static struct nvkm_oclass nv40_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0x40), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fifo_context_ctor, - .dtor = _nouveau_fifo_context_dtor, - .init = _nouveau_fifo_context_init, - .fini = _nouveau_fifo_context_fini, - .rd32 = _nouveau_fifo_context_rd32, - .wr32 = _nouveau_fifo_context_wr32, + .dtor = _nvkm_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, }, }; @@ -271,22 +265,22 @@ nv40_fifo_cclass = { ******************************************************************************/ static int -nv40_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_instmem_priv *imem = nv04_instmem(parent); struct nv04_fifo_priv *priv; int ret; - ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); *pobject = nv_object(priv); if (ret) return ret; - nouveau_ramht_ref(imem->ramht, &priv->ramht); - nouveau_gpuobj_ref(imem->ramro, &priv->ramro); - nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); + nvkm_ramht_ref(imem->ramht, &priv->ramht); + nvkm_gpuobj_ref(imem->ramro, &priv->ramro); + nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); nv_subdev(priv)->unit = 0x00000100; nv_subdev(priv)->intr = nv04_fifo_intr; @@ -299,13 +293,13 @@ nv40_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } static int -nv40_fifo_init(struct nouveau_object *object) +nv40_fifo_init(struct nvkm_object *object) { struct nv04_fifo_priv *priv = (void *)object; - struct nouveau_fb *pfb = nouveau_fb(object); + struct nvkm_fb *pfb = nvkm_fb(object); int ret; - ret = nouveau_fifo_init(&priv->base); + ret = nvkm_fifo_init(&priv->base); if (ret) return ret; @@ -350,13 +344,13 @@ nv40_fifo_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * -nv40_fifo_oclass = &(struct nouveau_oclass) { +struct nvkm_oclass * +nv40_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0x40), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv40_fifo_ctor, .dtor = nv04_fifo_dtor, .init = nv40_fifo_init, - .fini = _nouveau_fifo_fini, + .fini = _nvkm_fifo_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c index 403fafc05072..f25f0fd0655d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c @@ -21,21 +21,18 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" +#include "nv04.h" #include <core/client.h> #include <core/engctx.h> #include <core/ramht.h> -#include <nvif/unpack.h> -#include <nvif/class.h> - -#include <subdev/timer.h> #include <subdev/bar.h> +#include <subdev/mmu.h> +#include <subdev/timer.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> - -#include "nv04.h" -#include "nv50.h" +#include <nvif/class.h> +#include <nvif/unpack.h> /******************************************************************************* * FIFO channel objects @@ -44,8 +41,8 @@ static void nv50_fifo_playlist_update_locked(struct nv50_fifo_priv *priv) { - struct nouveau_bar *bar = nouveau_bar(priv); - struct nouveau_gpuobj *cur; + struct nvkm_bar *bar = nvkm_bar(priv); + struct nvkm_gpuobj *cur; int i, p; cur = priv->playlist[priv->cur_playlist]; @@ -72,12 +69,11 @@ nv50_fifo_playlist_update(struct nv50_fifo_priv *priv) } static int -nv50_fifo_context_attach(struct nouveau_object *parent, - struct nouveau_object *object) +nv50_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent->parent; - struct nouveau_gpuobj *ectx = (void *)object; + struct nvkm_gpuobj *ectx = (void *)object; u64 limit = ectx->addr + ectx->size - 1; u64 start = ectx->addr; u32 addr; @@ -103,10 +99,10 @@ nv50_fifo_context_attach(struct nouveau_object *parent, } static int -nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend, - struct nouveau_object *object) +nv50_fifo_context_detach(struct nvkm_object *parent, bool suspend, + struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_priv *priv = (void *)parent->engine; struct nv50_fifo_base *base = (void *)parent->parent; struct nv50_fifo_chan *chan = (void *)parent; @@ -139,7 +135,7 @@ nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend, nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12); if (!nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff)) { nv_error(priv, "channel %d [%s] unload timeout\n", - chan->base.chid, nouveau_client_name(chan)); + chan->base.chid, nvkm_client_name(chan)); if (suspend) ret = -EBUSY; } @@ -159,8 +155,8 @@ nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend, } static int -nv50_fifo_object_attach(struct nouveau_object *parent, - struct nouveau_object *object, u32 handle) +nv50_fifo_object_attach(struct nvkm_object *parent, + struct nvkm_object *object, u32 handle) { struct nv50_fifo_chan *chan = (void *)parent; u32 context; @@ -179,26 +175,25 @@ nv50_fifo_object_attach(struct nouveau_object *parent, return -EINVAL; } - return nouveau_ramht_insert(chan->ramht, 0, handle, context); + return nvkm_ramht_insert(chan->ramht, 0, handle, context); } void -nv50_fifo_object_detach(struct nouveau_object *parent, int cookie) +nv50_fifo_object_detach(struct nvkm_object *parent, int cookie) { struct nv50_fifo_chan *chan = (void *)parent; - nouveau_ramht_remove(chan->ramht, cookie); + nvkm_ramht_remove(chan->ramht, cookie); } static int -nv50_fifo_chan_ctor_dma(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv03_channel_dma_v0 v0; } *args = data; - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent; struct nv50_fifo_chan *chan; int ret; @@ -211,12 +206,12 @@ nv50_fifo_chan_ctor_dma(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x2000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, + 0x2000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG), &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -228,8 +223,8 @@ nv50_fifo_chan_ctor_dma(struct nouveau_object *parent, nv_parent(chan)->object_attach = nv50_fifo_object_attach; nv_parent(chan)->object_detach = nv50_fifo_object_detach; - ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, - &chan->ramht); + ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, + &chan->ramht); if (ret) return ret; @@ -252,15 +247,14 @@ nv50_fifo_chan_ctor_dma(struct nouveau_object *parent, } static int -nv50_fifo_chan_ctor_ind(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv50_channel_gpfifo_v0 v0; } *args = data; - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent; struct nv50_fifo_chan *chan; u64 ioffset, ilength; @@ -275,12 +269,12 @@ nv50_fifo_chan_ctor_ind(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x2000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, + 0x2000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG), &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -292,8 +286,8 @@ nv50_fifo_chan_ctor_ind(struct nouveau_object *parent, nv_parent(chan)->object_attach = nv50_fifo_object_attach; nv_parent(chan)->object_detach = nv50_fifo_object_detach; - ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, - &chan->ramht); + ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, + &chan->ramht); if (ret) return ret; @@ -316,24 +310,24 @@ nv50_fifo_chan_ctor_ind(struct nouveau_object *parent, } void -nv50_fifo_chan_dtor(struct nouveau_object *object) +nv50_fifo_chan_dtor(struct nvkm_object *object) { struct nv50_fifo_chan *chan = (void *)object; - nouveau_ramht_ref(NULL, &chan->ramht); - nouveau_fifo_channel_destroy(&chan->base); + nvkm_ramht_ref(NULL, &chan->ramht); + nvkm_fifo_channel_destroy(&chan->base); } static int -nv50_fifo_chan_init(struct nouveau_object *object) +nv50_fifo_chan_init(struct nvkm_object *object) { struct nv50_fifo_priv *priv = (void *)object->engine; struct nv50_fifo_base *base = (void *)object->parent; struct nv50_fifo_chan *chan = (void *)object; - struct nouveau_gpuobj *ramfc = base->ramfc; + struct nvkm_gpuobj *ramfc = base->ramfc; u32 chid = chan->base.chid; int ret; - ret = nouveau_fifo_channel_init(&chan->base); + ret = nvkm_fifo_channel_init(&chan->base); if (ret) return ret; @@ -343,7 +337,7 @@ nv50_fifo_chan_init(struct nouveau_object *object) } int -nv50_fifo_chan_fini(struct nouveau_object *object, bool suspend) +nv50_fifo_chan_fini(struct nvkm_object *object, bool suspend) { struct nv50_fifo_priv *priv = (void *)object->engine; struct nv50_fifo_chan *chan = (void *)object; @@ -354,34 +348,34 @@ nv50_fifo_chan_fini(struct nouveau_object *object, bool suspend) nv50_fifo_playlist_update(priv); nv_wr32(priv, 0x002600 + (chid * 4), 0x00000000); - return nouveau_fifo_channel_fini(&chan->base, suspend); + return nvkm_fifo_channel_fini(&chan->base, suspend); } -static struct nouveau_ofuncs +static struct nvkm_ofuncs nv50_fifo_ofuncs_dma = { .ctor = nv50_fifo_chan_ctor_dma, .dtor = nv50_fifo_chan_dtor, .init = nv50_fifo_chan_init, .fini = nv50_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_ofuncs +static struct nvkm_ofuncs nv50_fifo_ofuncs_ind = { .ctor = nv50_fifo_chan_ctor_ind, .dtor = nv50_fifo_chan_dtor, .init = nv50_fifo_chan_init, .fini = nv50_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_oclass +static struct nvkm_oclass nv50_fifo_sclass[] = { { NV50_CHANNEL_DMA, &nv50_fifo_ofuncs_dma }, { NV50_CHANNEL_GPFIFO, &nv50_fifo_ofuncs_ind }, @@ -393,36 +387,35 @@ nv50_fifo_sclass[] = { ******************************************************************************/ static int -nv50_fifo_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_fifo_base *base; int ret; - ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000, - 0x1000, NVOBJ_FLAG_HEAP, &base); + ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000, + 0x1000, NVOBJ_FLAG_HEAP, &base); *pobject = nv_object(base); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc); + ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0200, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1200, 0, - NVOBJ_FLAG_ZERO_ALLOC, &base->eng); + ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x1200, 0, + NVOBJ_FLAG_ZERO_ALLOC, &base->eng); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, 0, - &base->pgd); + ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, 0, + &base->pgd); if (ret) return ret; - ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd); + ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); if (ret) return ret; @@ -430,27 +423,27 @@ nv50_fifo_context_ctor(struct nouveau_object *parent, } void -nv50_fifo_context_dtor(struct nouveau_object *object) +nv50_fifo_context_dtor(struct nvkm_object *object) { struct nv50_fifo_base *base = (void *)object; - nouveau_vm_ref(NULL, &base->vm, base->pgd); - nouveau_gpuobj_ref(NULL, &base->pgd); - nouveau_gpuobj_ref(NULL, &base->eng); - nouveau_gpuobj_ref(NULL, &base->ramfc); - nouveau_gpuobj_ref(NULL, &base->cache); - nouveau_fifo_context_destroy(&base->base); + nvkm_vm_ref(NULL, &base->vm, base->pgd); + nvkm_gpuobj_ref(NULL, &base->pgd); + nvkm_gpuobj_ref(NULL, &base->eng); + nvkm_gpuobj_ref(NULL, &base->ramfc); + nvkm_gpuobj_ref(NULL, &base->cache); + nvkm_fifo_context_destroy(&base->base); } -static struct nouveau_oclass +static struct nvkm_oclass nv50_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_fifo_context_ctor, .dtor = nv50_fifo_context_dtor, - .init = _nouveau_fifo_context_init, - .fini = _nouveau_fifo_context_fini, - .rd32 = _nouveau_fifo_context_rd32, - .wr32 = _nouveau_fifo_context_wr32, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, }, }; @@ -459,25 +452,25 @@ nv50_fifo_cclass = { ******************************************************************************/ static int -nv50_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_fifo_priv *priv; int ret; - ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv); + ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, - &priv->playlist[0]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, + &priv->playlist[0]); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, - &priv->playlist[1]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, + &priv->playlist[1]); if (ret) return ret; @@ -491,23 +484,23 @@ nv50_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } void -nv50_fifo_dtor(struct nouveau_object *object) +nv50_fifo_dtor(struct nvkm_object *object) { struct nv50_fifo_priv *priv = (void *)object; - nouveau_gpuobj_ref(NULL, &priv->playlist[1]); - nouveau_gpuobj_ref(NULL, &priv->playlist[0]); + nvkm_gpuobj_ref(NULL, &priv->playlist[1]); + nvkm_gpuobj_ref(NULL, &priv->playlist[0]); - nouveau_fifo_destroy(&priv->base); + nvkm_fifo_destroy(&priv->base); } int -nv50_fifo_init(struct nouveau_object *object) +nv50_fifo_init(struct nvkm_object *object) { struct nv50_fifo_priv *priv = (void *)object; int ret, i; - ret = nouveau_fifo_init(&priv->base); + ret = nvkm_fifo_init(&priv->base); if (ret) return ret; @@ -529,13 +522,13 @@ nv50_fifo_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * -nv50_fifo_oclass = &(struct nouveau_oclass) { +struct nvkm_oclass * +nv50_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_fifo_ctor, .dtor = nv50_fifo_dtor, .init = nv50_fifo_init, - .fini = _nouveau_fifo_fini, + .fini = _nvkm_fifo_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h index 3a9ceb315c20..09ed93c66567 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h @@ -1,36 +1,36 @@ #ifndef __NV50_FIFO_H__ #define __NV50_FIFO_H__ +#include <engine/fifo.h> struct nv50_fifo_priv { - struct nouveau_fifo base; - struct nouveau_gpuobj *playlist[2]; + struct nvkm_fifo base; + struct nvkm_gpuobj *playlist[2]; int cur_playlist; }; struct nv50_fifo_base { - struct nouveau_fifo_base base; - struct nouveau_gpuobj *ramfc; - struct nouveau_gpuobj *cache; - struct nouveau_gpuobj *eng; - struct nouveau_gpuobj *pgd; - struct nouveau_vm *vm; + struct nvkm_fifo_base base; + struct nvkm_gpuobj *ramfc; + struct nvkm_gpuobj *cache; + struct nvkm_gpuobj *eng; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; }; struct nv50_fifo_chan { - struct nouveau_fifo_chan base; + struct nvkm_fifo_chan base; u32 subc[8]; - struct nouveau_ramht *ramht; + struct nvkm_ramht *ramht; }; void nv50_fifo_playlist_update(struct nv50_fifo_priv *); -void nv50_fifo_object_detach(struct nouveau_object *, int); -void nv50_fifo_chan_dtor(struct nouveau_object *); -int nv50_fifo_chan_fini(struct nouveau_object *, bool); +void nv50_fifo_object_detach(struct nvkm_object *, int); +void nv50_fifo_chan_dtor(struct nvkm_object *); +int nv50_fifo_chan_fini(struct nvkm_object *, bool); -void nv50_fifo_context_dtor(struct nouveau_object *); - -void nv50_fifo_dtor(struct nouveau_object *); -int nv50_fifo_init(struct nouveau_object *); +void nv50_fifo_context_dtor(struct nvkm_object *); +void nv50_fifo_dtor(struct nvkm_object *); +int nv50_fifo_init(struct nvkm_object *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.h deleted file mode 100644 index e96b32bb1bbc..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __NVKM_FIFO_NVE0_H__ -#define __NVKM_FIFO_NVE0_H__ - -#include <engine/fifo.h> - -int nve0_fifo_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nve0_fifo_dtor(struct nouveau_object *); -int nve0_fifo_init(struct nouveau_object *); -int nve0_fifo_fini(struct nouveau_object *, bool); - -struct nve0_fifo_impl { - struct nouveau_oclass base; - u32 channels; -}; - -#endif |
