blob: 38de76365c020cc7590927bc7110b18ea9e2383f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
|
/*
* Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <timer.h>
#include <os.h>
/* system timer offset in ms */
static unsigned long sandbox_timer_offset;
void sandbox_timer_add_offset(unsigned long offset)
{
sandbox_timer_offset += offset;
}
static int sandbox_timer_get_count(struct udevice *dev, unsigned long *count)
{
*count = os_get_nsec() / 1000 + sandbox_timer_offset * 1000;
return 0;
}
static int sandbox_timer_probe(struct udevice *dev)
{
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
uc_priv->clock_rate = 1000000;
return 0;
}
static const struct timer_ops sandbox_timer_ops = {
.get_count = sandbox_timer_get_count,
};
static const struct udevice_id sandbox_timer_ids[] = {
{ .compatible = "sandbox,timer" },
{ }
};
U_BOOT_DRIVER(sandbox_timer) = {
.name = "sandbox_timer",
.id = UCLASS_TIMER,
.of_match = sandbox_timer_ids,
.probe = sandbox_timer_probe,
.ops = &sandbox_timer_ops,
.flags = DM_FLAG_PRE_RELOC,
};
|
