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/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 6.3 EDK_Gmm.12.3
*/
/* System Clock Frequency */
#define XILINX_CLOCK_FREQ 100000000
/* Microblaze is microblaze_0 */
#define XILINX_FSL_NUMBER 2
/* Interrupt controller is intc_0 */
#define XILINX_INTC_BASEADDR 0x41200000
#define XILINX_INTC_NUM_INTR_INPUTS 4
/* Timer pheriphery is opb_timer_0 */
#define XILINX_TIMER_BASEADDR 0x41c00000
#define XILINX_TIMER_IRQ 0
/* Uart pheriphery is console_uart */
#define XILINX_UART_BASEADDR 0x40600000
#define XILINX_UART_BAUDRATE 115200
/* GPIO is opb_gpio_0*/
#define XILINX_GPIO_BASEADDR 0x90000000
/* Flash Memory is opb_emc_0 */
#define XILINX_FLASH_START 0x2c000000
#define XILINX_FLASH_SIZE 0x00800000
/* Main Memory is plb_ddr_0 */
#define XILINX_RAM_START 0x28000000
#define XILINX_RAM_SIZE 0x04000000
/* Sysace Controller is opb_sysace_0 */
#define XILINX_SYSACE_BASEADDR 0x41800000
#define XILINX_SYSACE_HIGHADDR 0x4180FFFF
#define XILINX_SYSACE_MEM_WIDTH 16
/* Ethernet controller is opb_ethernet_0 */
#define XPAR_XEMAC_NUM_INSTANCES 1
#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
#define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000
#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0fFFF
#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
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