blob: 2cba7169e4e464f8e58abfe157bb1859282a3fdf (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
|
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2012
* Markus Hubig <mhubig@imko.de>
* IMKO GmbH <www.imko.de>
*
* Copyright (C) 2013 DENX Software Engineering, hs@denx.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <watchdog.h>
void at91_phy_reset(void)
{
unsigned long erstl;
unsigned long start = get_timer(0);
unsigned long const timeout = 1000; /* 1000ms */
at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
/*
* Need to reset PHY -> 500ms reset
* Reset PHY by pulling the NRST line for 500ms to low. To do so
* disable user reset for low level on NRST pin and poll the NRST
* level in reset status register.
*/
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
AT91_RSTC_MR_URSTEN, &rstc->mr);
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end of hardware reset */
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
/* avoid shutdown by watchdog */
WATCHDOG_RESET();
mdelay(10);
/* timeout for not getting stuck in an endless loop */
if (get_timer(start) >= timeout) {
puts("*** ERROR: Timeout waiting for PHY reset!\n");
break;
}
};
/* Restore NRST value */
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
}
|
