1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
|
/*
* sys_info.c
*
* System information functions
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* Derived from Beagle Board and 3430 SDP code by
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <power/tps65910.h>
struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
/**
* get_cpu_rev(void) - extract rev info
*/
u32 get_cpu_rev(void)
{
u32 id;
u32 rev;
id = readl(DEVICE_ID);
rev = (id >> 28) & 0xff;
return rev;
}
/**
* get_cpu_type(void) - extract cpu info
*/
u32 get_cpu_type(void)
{
u32 id = 0;
u32 partnum;
id = readl(DEVICE_ID);
partnum = (id >> 12) & 0xffff;
return partnum;
}
/**
* get_board_rev() - setup to pass kernel board revision information
* returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
*/
u32 get_board_rev(void)
{
return BOARD_REV_ID;
}
/**
* get_device_type(): tell if GP/HS/EMU/TST
*/
u32 get_device_type(void)
{
int mode;
mode = readl(&cstat->statusreg) & (DEVICE_MASK);
return mode >>= 8;
}
/**
* get_sysboot_value(void) - return SYS_BOOT[4:0]
*/
u32 get_sysboot_value(void)
{
int mode;
mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
return mode;
}
#ifdef CONFIG_DISPLAY_CPUINFO
static char *cpu_revs[] = {
"1.0",
"2.0",
"2.1"};
static char *dev_types[] = {
"TST",
"EMU",
"HS",
"GP"};
/**
* Print CPU information
*/
int print_cpuinfo(void)
{
char *cpu_s, *sec_s, *rev_s;
switch (get_cpu_type()) {
case AM335X:
cpu_s = "AM335X";
break;
case TI81XX:
cpu_s = "TI81XX";
break;
default:
cpu_s = "Unknown CPU type";
break;
}
if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
rev_s = cpu_revs[get_cpu_rev()];
else
rev_s = "?";
if (get_device_type() < ARRAY_SIZE(dev_types))
sec_s = dev_types[get_device_type()];
else
sec_s = "?";
printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s);
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
#ifdef CONFIG_AM33XX
int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
{
int sil_rev;
sil_rev = readl(&cdev->deviceid) >> 28;
if (sil_rev == 1)
/* PG 2.0, efuse may not be set. */
return MPUPLL_M_800;
else if (sil_rev >= 2) {
/* Check what the efuse says our max speed is. */
int efuse_arm_mpu_max_freq;
efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
case AM335X_ZCZ_1000:
return MPUPLL_M_1000;
case AM335X_ZCZ_800:
return MPUPLL_M_800;
case AM335X_ZCZ_720:
return MPUPLL_M_720;
case AM335X_ZCZ_600:
case AM335X_ZCE_600:
return MPUPLL_M_600;
case AM335X_ZCZ_300:
case AM335X_ZCE_300:
return MPUPLL_M_300;
}
}
/* PG 1.0 or otherwise unknown, use the PG1.0 max */
return MPUPLL_M_720;
}
int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
{
/* For PG2.1 and later, we have one set of values. */
if (sil_rev >= 2) {
switch (frequency) {
case MPUPLL_M_1000:
return TPS65910_OP_REG_SEL_1_3_2_5;
case MPUPLL_M_800:
return TPS65910_OP_REG_SEL_1_2_6;
case MPUPLL_M_720:
return TPS65910_OP_REG_SEL_1_2_0;
case MPUPLL_M_600:
case MPUPLL_M_300:
return TPS65910_OP_REG_SEL_1_1_3;
}
}
/* Default to PG1.0/PG2.0 values. */
return TPS65910_OP_REG_SEL_1_1_3;
}
#endif
|
