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* ehci-hcd: Add init_after_resetMateusz Kulikowski2016-04-012-0/+7
| | | | | | | | | | | | Some host controllers need addidional initialization after ehci_reset() In non-dm implementation it is possible to use CONFIG_EHCI_HCD_INIT_AFTER_RESET. This patch adds similar option to ehci drivers using dm. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* mmc: Add support for Qualcomm SDHCI controllerMateusz Kulikowski2016-04-013-0/+190
| | | | | | | | | | | Add support for SD/eMMC controller present on some Qualcomm Snapdragon devices. This controller implements SDHCI 2.0 interface but requires vendor-specific initialization. Driver works in PIO mode as ADMA is not supported by U-Boot (yet). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* gpio: Add support for Qualcomm gpio controllerMateusz Kulikowski2016-04-013-0/+148
| | | | | | | | | | Add support for gpio controllers on Qualcomm Snapdragon devices. This devices are usually called Top Level Mode Multiplexing in Qualcomm documentation. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* serial: Add support for Qualcomm serial portMateusz Kulikowski2016-04-013-0/+226
| | | | | | | | | This driver works in "new" Data Mover UART mode, so will be compatible with modern Qualcomm chips only. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* smsc95xx: fix operation on 64-bit systemsStephen Warren2016-04-011-2/+2
| | | | | | | | | | | | smsc95xx_read_reg() should calculate sizeof(*data) not sizeof(data) since data is a pointer, and the value pointed at is being transferred over USB, not the value of the pointer. This fixes operation of the driver in 64-bit builds, such as the Raspberry Pi 3. Reported-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* fastboot: allow retrieving fastboot variables from envRob Herring2016-04-011-2/+10
| | | | | | | | | | | | | | | | | | | | Some boards need to expose device specific variable through fastboot (to adpat the flashing script depending on hardware revision for example). Provide a way to expose custom fastboot variables. Note that all variables meant to be exposed through fastboot should be be prefixed with 'fastboot.', the variable should not exceed 32 bytes (including the prefix and the trailing '\0') and the variable content should fit in the response buffer (60 bytes excluding the 'OKAY' prefix and the trailing '\0'). Signed-off-by: Rob Herring <rob.herring@linaro.org> [Boris Brezillon: add a commit message] Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Steve Rae <srae@broadcom.com>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-04-019-17/+118
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| * sunxi: Add support for Allwinner A64 SoCsSiarhei Siamashka2016-04-012-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A64 SoC is used in the Pine64. This patch adds all bits necessary to compile U-Boot for it running in AArch64 mode. Unfortunately SPL is not ready yet due to legal problems, so we need to boot using the binary boot0 for now. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> [agraf: remove SPL code, move to AArch64] Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Explicitly cast u32 pointer conversionsAlexander Graf2016-04-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | Some parts of the sunxi code cast explicitly between u32 values and pointers. This is not a problem in practice, because all 64bit SoCs today only use the lower 32 bits for their phyical address space. But we need to make sure that the compiler is sure this is not an accident as well. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: ohci: Add A83T compatibleChen-Yu Tsai2016-03-311-0/+1
| | | | | | | | | | | | | | | | We have a separate compatible for almost each SoC. Add one for the A83T. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: ehci: Add A83T compatibleChen-Yu Tsai2016-03-311-0/+1
| | | | | | | | | | | | | | | | We have a separate compatible for almost each SoC. Add one for the A83T. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * power: axp818: Add support for FLDOsChen-Yu Tsai2016-03-312-0/+61
| | | | | | | | | | | | | | | | | | The FLDOs on AXP818 PMIC normally provide power to CPUS and USB HSIC PHY on the A83T/H8. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * power: axp818: Fix DCDC5 default voltageChen-Yu Tsai2016-03-311-2/+1
| | | | | | | | | | | | | | | | | | | | | | DCDC5 is designed to supply VCC-DRAM, which is normally 1.5V for DDR3, 1.35V for DDR3L, and 1.2V for LPDDR3. Also remove CONFIG_AXP_DCDC5_VOLT from h8_homlet_v2_defconfig. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: axp: Generalize register macros for VBUS drive GPIOChen-Yu Tsai2016-03-311-11/+14
| | | | | | | | | | | | | | | | | | VBUS drive is supported on AXP221 and later PMICs. Rework the macros so we can support this on later PMICs without too much work. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * musb: sunxi: Add support for A83TChen-Yu Tsai2016-03-311-1/+1
| | | | | | | | | | | | | | | | | | | | Like the Allwinner A33 SoC, the A83T is missing the config register from the musb USB DRD hardware block. Use a known working value for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * net: phy: Optionally force master mode for RTL PHYMichael Haas2016-03-312-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces CONFIG_RTL8211X_PHY_FORCE_MASTER. If this define is set, RTL8211x PHYs (except for the RTL8211F) will have their 1000BASE-T master/slave autonegotiation disabled and forced to master mode. This is helpful for PHYs like the RTL8211C which produce unstable links in slave mode. Such problems have been found on the A20-Olimex-SOM-EVB and A20-OLinuXino-Lime2. There is no proper way to identify affected PHYs in software as the RTL8211C shares its UID with the RTL8211B. Thus, this fix requires the introduction of an #ifdef. CC: fradav@gmail.com CC: merker@debian.org CC: hdegoede@redhat.com CC: ijc@hellion.org.uk CC: joe.hershberger@ni.com Signed-off-by: Michael Haas <haas@computerlinguist.org> Tested-by: Karsten Merker <merker@debian.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | pinctrl: uniphier: support UniPhier PH1-LD11 pinctrl driverMasahiro Yamada2016-04-012-6/+7
| | | | | | | | | | | | | | | | The pinmux of PH1-LD11 is almost a subset of that of PH1-LD20 (as far as used in boot-loader), so this commit makes the driver shared between the two SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl driverMasahiro Yamada2016-04-013-0/+120
| | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD20 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | pinctrl: uniphier: support per-pin input enable for new SoCsMasahiro Yamada2016-04-012-1/+28
| | | | | | | | | | | | | | | | Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input signal gating for each pin. (While, existing ones only support it per pin-group.) This commit prepares the core part for that. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | pinctrl: uniphier: introduce capability flagMasahiro Yamada2016-04-018-27/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core part of the UniPhier pinctrl driver needs to support a new capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens because pinctrl drivers include really SoC-specific stuff. This commit intends to tidy up SoC-specific parameters of the existing drivers before adding new ones. Having flags would be better than adding new members every time a new SoC-specific capability comes up. At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE. This capability (I'd say rather quirk) was added for PH1-Pro4 and PH1-Pro5 as requirement from our customer. For those SoCs, one pin-mux setting is controlled by the combination of two separate registers; the LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4). Because it is impossible to update two separate registers atomically, the LOAD_PINCTRL register should be set in order to make the pin-mux settings really effective. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | pinctrl: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-011-6/+3
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | mmc: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-011-3/+6
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | gpio: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-011-5/+3
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | i2c: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-012-13/+10
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | clk: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-011-6/+3
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | serial: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-011-3/+5
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | mtd: nand: denali: max_banks calculation changed in revision 5.1Graham Moore2016-04-012-1/+12
|/ | | | | | | | | | | | | | Read Denali hardware revision number and use it to calculate max_banks, The encoding of max_banks changed in Denali revision 5.1. [ Linux commit : 271707b1d817f5104e02b2bd1bab43f0c8759418 ] Signed-off-by: Graham Moore <grmoore@opensource.altera.com> [Brian: parentheses around macro arg] Signed-off-by: Brian Norris <computersforpeace@gmail.com> [Masahiro: import from Linux and adjust ioread32() to readl() ] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-03-295-6/+21
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| * crypto/fsl: Make CAAM transactions cacheableSaksham Jain2016-03-292-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit solves CAAM coherency issue on ls2080. When caches are enabled and CAAM's DMA's AXI transcations are not made cacheable, Core reads/writes data from/to caches and CAAM does from main memory. This forces data flushes to synchronize various data structures. But even if any data in proximity of these structures is read by core, these structures again are fetched in caches. To avoid this problem, either all the data that CAAM accesses can be made cache line aligned or CAAM transcations can be made cacheable. So, this commit makes CAAM transcations as write back with write and read allocate. Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * crypto/fsl: Correct 64-bit write when MMU disabledSaksham Jain2016-03-291-4/+3
| | | | | | | | | | | | | | | | | | | | | | When MMU is disabled, 64-bit write must be aligned at 64-bit boundary. Becaue the memory location is not guaranteed to be 64-bit aligned, the 64-bit write needs to be split into two 32-bit writes to avoid the alignment exception. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver: net: fsl-mc: Check NULL before pointer dereferencePrabhakar Kushwaha2016-03-291-1/+1
| | | | | | | | | | | | | | | | | | | | NULL pointer should be checked before any dereference. This patch move memest after the NULL pointer check. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reported-by: Jose Rivera <german.rivera@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver: net: fsl-mc: Free dflt_dpio pointer after its usagePrabhakar Kushwaha2016-03-281-1/+1
| | | | | | | | | | | | | | | | Free dflt_dpio pointer after its usage during error handling Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reported-by: Jose Rivera <german.rivera@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | omap24xx_i2c: Implement CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOWGuy Thouret2016-03-281-0/+34
| | | | | | | | | | Signed-off-by: Guy Thouret <guy.thouret@wems.co.uk> Cc: Heiko Schocher <hs@denx.de>
* | dm: i2c: mxc_i2c: implement i2c_idle_busPeng Fan2016-03-281-9/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement i2c_idle_bus in driver, then setup_i2c can be dropped for boards which enable DM_I2C/DM_GPIO/PINCTRL. The i2c_idle_bus force bus idle flow follows setup_i2c in arch/arm/imx-common/i2c-mxv7.c This patch is an implementation following linux kernel patch: " commit 1c4b6c3bcf30d0804db0d0647d8ebeb862c6f7e5 Author: Gao Pan <b54642@freescale.com> Date: Fri Oct 23 20:28:54 2015 +0800 i2c: imx: implement bus recovery Implement bus recovery methods for i2c-imx so we can recover from situations where SCL/SDA are stuck low. Once i2c bus SCL/SDA are stuck low during transfer, config the i2c pinctrl to gpio mode by calling pinctrl sleep set function, and then use GPIO to emulate the i2c protocol to send nine dummy clock to recover i2c device. After recovery, set i2c pinctrl to default group setting. " See Documentation/devicetree/bindings/i2c/i2c-imx.txt for detailed description. 1. Introuduce scl_gpio/sda_gpio/bus in mxc_i2c_bus. 2. Discard the __weak attribute for i2c_idle_bus and implement it, since we have pinctrl driver/driver model gpio driver. We can use device tree, but not let board code to do this. 3. gpio state for mxc_i2c is not a must, but it is recommended. If there is no gpio state, driver will give tips, but not fail. 4. The i2c controller was first probed, default pinctrl state will be used, so when need to use gpio function, need to do "pinctrl_select_state(dev, "gpio")" and after force bus idle, need to switch back "pinctrl_select_state(dev, "default")". This is example about how to use the gpio force bus idle function: " &i2c1 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; status = "okay"; [....] }; [.....] pinctrl_i2c1_gpio: i2c1grp_gpio { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 >; }; " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com>
* | Revert "pxa_lcd: make driver cache-aware"Tom Rini2016-03-271-16/+0
| | | | | | | | | | | | This reverts commit 59deb7fe8d23c8ec2b659d99323ec4a2ec19148a. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Revert "pxa_lcd: invert colors for Zipit Z2 to get white on black palette"Tom Rini2016-03-271-1/+1
| | | | | | | | | | | | This reverts commit 3bc8ffd9cb774feceefc7bdebe9353fcea071343. Signed-off-by: Tom Rini <trini@konsulko.com>
* | cfi_flash: return device into read array mode after reading statusVasily Khoruzhick2016-03-271-0/+2
| | | | | | | | | | | | | | | | Otherwise flash remains in read status mode and it's not possible to access data on flash. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
* | pxa_lcd: make driver cache-awareVasily Khoruzhick2016-03-271-0/+16
| | | | | | | | Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
* | pxa_lcd: invert colors for Zipit Z2 to get white on black paletteVasily Khoruzhick2016-03-271-1/+1
| | | | | | | | Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
* | zipitz2: enable LCD rotationVasily Khoruzhick2016-03-271-0/+1
| | | | | | | | | | | | | | z2's screen is rotated by 270 degrees Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* | serial: add BCM283x mini UART driverStephen Warren2016-03-272-0/+141
| | | | | | | | | | | | | | | | The RPi3 typically uses the regular UART for high-speed communication with the Bluetooth device, leaving us the mini UART to use for the serial console. Add support for this UART so we can use it. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | net: rtl8169: Fix build error when DEBUG is onBin Meng2016-03-271-5/+5
| | | | | | | | | | | | | | | | | | When DEBUG_RTL8169 is on, a build error occurs in function 'rtl_init': error: 'dev' undeclared. Fix this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | mmc: Print send_cmd response only when return value is zeroBin Meng2016-03-271-38/+42
| | | | | | | | | | | | | | | | send_cmd response is valid only when no error happened. If an error occured, let mmc_send_cmd() print the return value to aid debugging. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | mmc: Fix switch..case indentionBin Meng2016-03-271-70/+70
| | | | | | | | | | | | | | Correct the indention level of switch..case statements. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Fix typo choosen in comments and printf logsAlexander Merkle2016-03-271-2/+2
| | | | | | | | | | | | | | | | Minor change: chosen is written with one "o". No code change here, only comment & printf. Signed-off-by: Alexander Merkle <alexander.merkle@lauterbach.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | mmc: bcm2835: fix 64-bit build warningStephen Warren2016-03-271-1/+1
| | | | | | | | | | | | | | | | Fixes: drivers/mmc/bcm2835_sdhci.c: In function ‘bcm2835_sdhci_init’: drivers/mmc/bcm2835_sdhci.c:181:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | bcm2835 video: Map fb as cachedAlexander Graf2016-03-271-0/+9
| | | | | | | | | | | | | | | | | | The bcm2835 frame buffer is in RAM, so we can easily map it as cached and gain all the glorious performance boost that brings with it. Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
* | stm32: stm32f4: move flash driver to mtd driver locationVikas Manocha2016-03-263-0/+175
| | | | | | | | | | | | | | Same flash driver can be used by other stm32 families like stm32f7. Better place for this driver would be mtd driver location. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | usb: gadget: Move CONFIG_USB_GADGET to KconfigSam Protsenko2016-03-252-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The description was borrowed from kernel. "tristate" type was changed to "bool" (I believe we don't support modules for u-boot yet, right?). CONFIG_USB_GADGET requires CONFIG_USB to be defined too, so add it along as well. Definitions were added to defconfig files in a way that "make savedefconfig" generates exactly the same file as used defconfig. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> [trini: Add zynq_zc702 conversion] Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-03-257-2/+234
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