Merge git://www.denx.de/git/u-boot-marvell

7 files changed, 234 insertions, 2 deletions

diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c
index 556f877039..ee05f57f43 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -305,8 +305,6 @@ int ddr3_init(void)
 		SAR1_CPU_CORE_OFFSET;
 	switch (soc_num) {
 	case 0x3:
-		reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET);
-		reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET);
 	case 0x1:
 		reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
 	case 0x0:
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 6aa24d4359..fec3fecbdf 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -17,5 +17,6 @@ obj-y += altera.o
 obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
 obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
 obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
+obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
 obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
 endif
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index a5bfe5dce1..135a3572a8 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -37,6 +37,9 @@ static const struct altera_fpga {
 	{ Altera_StratixII, "StratixII", StratixII_load,
 	  StratixII_dump, StratixII_info },
 #endif
+#if defined(CONFIG_FPGA_STRATIX_V)
+	{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
+#endif
 #if defined(CONFIG_FPGA_SOCFPGA)
 	{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
 #endif
diff --git a/drivers/fpga/stratixv.c b/drivers/fpga/stratixv.c
new file mode 100644
index 0000000000..cc035eb2a1
--- /dev/null
+++ b/drivers/fpga/stratixv.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <altera.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+/* Write the RBF data to FPGA via SPI */
+static int program_write(int spi_bus, int spi_dev, const void *rbf_data,
+			 unsigned long rbf_size)
+{
+	struct spi_slave *slave;
+	int ret;
+
+	debug("%s (%d): data=%p size=%ld\n",
+	      __func__, __LINE__, rbf_data, rbf_size);
+
+	/* FIXME: How to get the max. SPI clock and SPI mode? */
+	slave = spi_setup_slave(spi_bus, spi_dev, 27777777, SPI_MODE_3);
+	if (!slave)
+		return -1;
+
+	if (spi_claim_bus(slave))
+		return -1;
+
+	ret = spi_xfer(slave, rbf_size * 8, rbf_data, (void *)rbf_data,
+		       SPI_XFER_BEGIN | SPI_XFER_END);
+
+	spi_release_bus(slave);
+
+	return ret;
+}
+
+/*
+ * This is the interface used by FPGA driver.
+ * Return 0 for sucess, non-zero for error.
+ */
+int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+	altera_board_specific_func *pfns = desc->iface_fns;
+	int cookie = desc->cookie;
+	int spi_bus;
+	int spi_dev;
+	int ret = 0;
+
+	if ((u32)rbf_data & 0x3) {
+		puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
+		return -EINVAL;
+	}
+
+	/* Run the pre configuration function if there is one */
+	if (pfns->pre)
+		(pfns->pre)(cookie);
+
+	/* Establish the initial state */
+	if (pfns->config) {
+		/* De-assert nCONFIG */
+		(pfns->config)(false, true, cookie);
+
+		/* nConfig minimum low pulse width is 2us */
+		udelay(200);
+
+		/* Assert nCONFIG */
+		(pfns->config)(true, true, cookie);
+
+		/* nCONFIG high to first rising clock on DCLK min 1506 us */
+		udelay(1600);
+	}
+
+	/* Write the RBF data to FPGA */
+	if (pfns->write) {
+		/*
+		 * Use board specific data function to write bitstream
+		 * into the FPGA
+		 */
+		ret = (pfns->write)(rbf_data, rbf_size, true, cookie);
+	} else {
+		/*
+		 * Use common SPI functions to write bitstream into the
+		 * FPGA
+		 */
+		spi_bus = COOKIE2SPI_BUS(cookie);
+		spi_dev = COOKIE2SPI_DEV(cookie);
+		ret = program_write(spi_bus, spi_dev, rbf_data, rbf_size);
+	}
+	if (ret)
+		return ret;
+
+	/* Check done pin */
+	if (pfns->done) {
+		ret = (pfns->done)(cookie);
+
+		if (ret)
+			printf("Error: DONE not set (ret=%d)!\n", ret);
+	}
+
+	return ret;
+}
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index a5da5e7e88..23113090b3 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -105,4 +105,11 @@ config PIC32_GPIO
 	help
 	  Say yes here to support Microchip PIC32 GPIOs.
 
+config MVEBU_GPIO
+	bool "Marvell MVEBU GPIO driver"
+	depends on DM_GPIO && ARCH_MVEBU
+	default y
+	help
+	  Say yes here to support Marvell MVEBU (Armada XP/38x) GPIOs.
+
 endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index e7b7ec45b7..ea6e2ede0d 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_ZYNQ_GPIO)		+= zynq_gpio.o
 obj-$(CONFIG_VYBRID_GPIO)	+= vybrid_gpio.o
 obj-$(CONFIG_HIKEY_GPIO)	+= hi6220_gpio.o
 obj-$(CONFIG_PIC32_GPIO)	+= pic32_gpio.o
+obj-$(CONFIG_MVEBU_GPIO)	+= mvebu_gpio.o
diff --git a/drivers/gpio/mvebu_gpio.c b/drivers/gpio/mvebu_gpio.c
new file mode 100644
index 0000000000..9564ce2b13
--- /dev/null
+++ b/drivers/gpio/mvebu_gpio.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MVEBU_GPIOS_PER_BANK	32
+
+struct mvebu_gpio_regs {
+	u32 data_out;
+	u32 io_conf;
+	u32 blink_en;
+	u32 in_pol;
+	u32 data_in;
+};
+
+struct mvebu_gpio_priv {
+	struct mvebu_gpio_regs *regs;
+	char name[2];
+};
+
+static int mvebu_gpio_direction_input(struct udevice *dev, unsigned int gpio)
+{
+	struct mvebu_gpio_priv *priv = dev_get_priv(dev);
+	struct mvebu_gpio_regs *regs = priv->regs;
+
+	setbits_le32(&regs->io_conf, BIT(gpio));
+
+	return 0;
+}
+
+static int mvebu_gpio_direction_output(struct udevice *dev, unsigned gpio,
+				       int value)
+{
+	struct mvebu_gpio_priv *priv = dev_get_priv(dev);
+	struct mvebu_gpio_regs *regs = priv->regs;
+
+	clrbits_le32(&regs->io_conf, BIT(gpio));
+
+	return 0;
+}
+
+static int mvebu_gpio_get_function(struct udevice *dev, unsigned gpio)
+{
+	struct mvebu_gpio_priv *priv = dev_get_priv(dev);
+	struct mvebu_gpio_regs *regs = priv->regs;
+	u32 val;
+
+	val = readl(&regs->io_conf) & BIT(gpio);
+	if (val)
+		return GPIOF_INPUT;
+	else
+		return GPIOF_OUTPUT;
+}
+
+static int mvebu_gpio_set_value(struct udevice *dev, unsigned gpio,
+				int value)
+{
+	struct mvebu_gpio_priv *priv = dev_get_priv(dev);
+	struct mvebu_gpio_regs *regs = priv->regs;
+
+	if (value)
+		setbits_le32(&regs->data_out, BIT(gpio));
+	else
+		clrbits_le32(&regs->data_out, BIT(gpio));
+
+	return 0;
+}
+
+static int mvebu_gpio_get_value(struct udevice *dev, unsigned gpio)
+{
+	struct mvebu_gpio_priv *priv = dev_get_priv(dev);
+	struct mvebu_gpio_regs *regs = priv->regs;
+
+	return !!(readl(&regs->data_in) & BIT(gpio));
+}
+
+static int mvebu_gpio_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct mvebu_gpio_priv *priv = dev_get_priv(dev);
+
+	priv->regs = (struct mvebu_gpio_regs *)dev_get_addr(dev);
+	uc_priv->gpio_count = MVEBU_GPIOS_PER_BANK;
+	priv->name[0] = 'A' + dev->req_seq;
+	uc_priv->bank_name = priv->name;
+
+	return 0;
+}
+
+static const struct dm_gpio_ops mvebu_gpio_ops = {
+	.direction_input	= mvebu_gpio_direction_input,
+	.direction_output	= mvebu_gpio_direction_output,
+	.get_function		= mvebu_gpio_get_function,
+	.get_value		= mvebu_gpio_get_value,
+	.set_value		= mvebu_gpio_set_value,
+};
+
+static const struct udevice_id mvebu_gpio_ids[] = {
+	{ .compatible = "marvell,orion-gpio" },
+	{ }
+};
+
+U_BOOT_DRIVER(gpio_mvebu) = {
+	.name			= "gpio_mvebu",
+	.id			= UCLASS_GPIO,
+	.of_match		= mvebu_gpio_ids,
+	.ops			= &mvebu_gpio_ops,
+	.probe			= mvebu_gpio_probe,
+	.priv_auto_alloc_size	= sizeof(struct mvebu_gpio_priv),
+};