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* ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1)Stefan Roese2007-10-311-1067/+0
| | | | | | | | | | This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (1) This patch renames the files from 440spe_pcie to 4xx_pcie Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Coding style cleanupStefan Roese2007-10-021-5/+5
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* [PPC440SPe] Improve PCIe configuration space accessGrzegorz Bernacki2007-09-071-24/+87
| | | | | | | | | | | | | - correct configuration space mapping - correct bus numbering - better access to config space Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the first device on the first bus. We now allow to configure up to 16 buses; also, scanning for devices behind the PCIe-PCIe bridge is supported, so peripheral devices farther in hierarchy can be identified. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* [PPC440SPe] Convert machine check exceptions handlingGrzegorz Bernacki2007-09-071-24/+35
| | | | | | | | | | | | | | | | Convert using fixup mechanism to suppressing MCK for the duration of config read/write transaction: while fixups work fine with the case of a precise exception, we identified a major drawback with this approach when there's an imprecise case. In this scenario there is the following race condition: the fixup is (by design) set to catch the instruction following the one actually causing the exception; if an interrupt (e.g. decrementer) happens between those two instructions, the ISR code is executed before the fixup handler the machine check is no longer protected by the fixup handler as it appears as within the ISR code. In consequence the fixup approach is being phased out and replaced with explicit suppressing of MCK during a PCIe config read/write cycle. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* [ppc440SPe] Graceful recovery from machine check during PCIe configurationGrzegorz Bernacki2007-08-021-4/+32
| | | | | | | | | | | During config transactions on the PCIe bus an attempt to scan for a non-existent device can lead to a machine check exception with certain peripheral devices. In order to avoid crashing in such scenarios the instrumented versions of the config cycle read routines are introduced, so the exceptions fixups framework can gracefully recover. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Rafal Jaworowski <raj@semihalf.com>
* [ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.ARafal Jaworowski2007-08-021-3/+8
| | | | | | | | | This brings back separate settings for PCIe bus numbers depending on chip revision, which got eliminated in 2b393b0f0af8402ef43b25c1968bfd29714ddffa commit. 440SPe rev. A does NOT work properly with the same settings as for the rev. B (no devices are seen on the bus during enumeration). Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
* [PATCH] Add support for AMCC Taishan PPC440GX eval boardStefan Roese2007-01-181-5/+3
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* PCIe endpoint support for AMCC Yucca 440SPe boardStefan Roese2006-08-291-23/+393
| | | | Patch by Tirumala R Marri, 26 Aug 2006
* Code cleanupWolfgang Denk2006-08-271-1/+1
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* Fix PCI-Express on PPC440SPe rev. A.Rafal Jaworowski2006-08-111-14/+13
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* Add support for PCI-Express on PPC440SPe (Yucca board).Rafal Jaworowski2006-08-101-0/+593
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