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* 85xx/p1_p2_rdb: Modify the CLK_CTRL value for DDR at 667MHzPoonam Aggrwal2010-06-291-1/+1
| | | | | | | | | | | Use a slighly larger value of CLK_CTRL for DDR at 667MHz which fixes random crashes while linux booting. Applicable for both NAND and NOR boot. Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data ratePoonam Aggrwal2009-10-271-2/+2
| | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/p1_p2rdb: Fix crash while configuring 32 bit DDR i/f for P1020RDB.Poonam Aggrwal2009-10-271-8/+8
| | | | | | | The data being modified was in NOR flash which caused the crash. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: 32bit DDR changes for P1020/P1011Poonam Aggrwal2009-09-241-5/+24
| | | | | | | | | | | | | The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010 where max DDR data width supported is 64bit. As a next step the DDR data width initialization would be made more dynamic with more flexibility from the board perspective and user choice. Going forward we would also remove the hardcodings for platforms with onboard memories and try to use the FSL SPD code for DDR initialization. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/8xxx: Remove ddr_pd_cntl register since it doesn't existKumar Gala2009-09-081-5/+0
| | | | | | | | The ddr_pd_cntl isn't defined in any reference manual and thus we wil remove especially since we set it to 0, which would most likely be its POR value. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add support for P2020RDB boardPoonam Aggrwal2009-08-281-0/+243
The code base adds P1 & P2 RDB platforms support. The folder and file names can cater to future SOCs of P1/P2 family. P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series. Tested following on P2020RDB: 1. eTSECs 2. DDR, NAND, NOR, I2C. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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