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* x86: ivybridge: Remove the dead codes that programs pci bridgeBin Meng2015-10-211-32/+0
* x86: Enable DM RTC support for all x86 boardsBin Meng2015-07-282-9/+24
* Kill unneeded #include <linux/kconfig.h>Masahiro Yamada2015-07-271-1/+0
* x86: Clean up lapic codesBin Meng2015-07-141-1/+1
* x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONSBin Meng2015-07-141-1/+0
* x86: Add multi-processor initSimon Glass2015-04-302-2/+3
* x86: ivybridge: Use reset_cpu()Simon Glass2015-04-293-15/+6
* x86: chromebook_link: dts: Add PCH and LPC devicesSimon Glass2015-04-182-2/+13
* dm: x86: Add a uclass for a Platform Controller HubSimon Glass2015-04-181-9/+0
* dm: x86: spi: Convert ICH SPI driver to driver modelSimon Glass2015-04-182-10/+14
* dm: x86: pci: Convert chromebook_link to use driver model for pciSimon Glass2015-04-184-65/+57
* x86: Split up arch_cpu_init()Simon Glass2015-04-161-0/+8
* x86: Add a x86_ prefix to the x86-specific PCI functionsSimon Glass2015-04-1614-163/+166
* x86: video: Allow video ROM execution to fall back to the other methodSimon Glass2015-02-051-1/+2
* x86: Rename MMCONF_BASE_ADDRESS and make it common across x86Simon Glass2015-02-051-1/+1
* x86: ivybridge: Drop the Kconfig MRC cache informationSimon Glass2015-01-241-28/+0
* x86: Implement a cache for Memory Reference Code parametersSimon Glass2015-01-243-0/+410
* x86: ivybridge: Update microcode early in bootSimon Glass2015-01-133-10/+34
* x86: ivybridge: Add a way to turn off the CARSimon Glass2015-01-131-0/+46
* x86: ivybridge: Request MTRRs for DRAM regionsSimon Glass2015-01-131-0/+10
* x86: ivybridge: Set up an MTRR for the video frame bufferSimon Glass2015-01-131-0/+7
* x86: Add support for MTRRsSimon Glass2015-01-131-6/+6
* x86: ivybridge: Drop support for ROM cachingSimon Glass2015-01-131-25/+0
* x86: ivybridge: Only run the Video BIOS when video is enabledSimon Glass2015-01-131-1/+8
* x86: Use consistent name XXX_ADDR for binary blob flash addressBin Meng2014-12-181-1/+1
* x86: Correct problems in the microcode loadingSimon Glass2014-12-181-10/+15
* x86: ivybridge: Update the microcodeSimon Glass2014-12-181-0/+2
* x86: Add post failure codes for bist and carBin Meng2014-12-131-0/+1
* x86: Add initial video device init for Intel GMASimon Glass2014-11-254-1/+925
* x86: ivybridge: Add northbridge init functionsSimon Glass2014-11-253-0/+191
* x86: Add init for model 206AX CPUSimon Glass2014-11-253-0/+521
* x86: ivybridge: Set up XHCI USBSimon Glass2014-11-252-0/+33
* x86: ivybridge: Set up EHCI USBSimon Glass2014-11-253-0/+32
* x86: ivybridge: Add SATA initSimon Glass2014-11-253-0/+246
* x86: ivybridge: Add additional LPC initSimon Glass2014-11-252-1/+528
* x86: ivybridge: Add PCH initSimon Glass2014-11-252-0/+124
* x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-253-0/+140
* x86: ivybridge: Implement SDRAM initSimon Glass2014-11-216-1/+1031
* x86: ivybridge: Add LAPIC supportSimon Glass2014-11-211-0/+3
* x86: ivybridge: Add early init for PCH devicesSimon Glass2014-11-213-0/+287
* x86: ivybridge: Perform Intel microcode update on bootSimon Glass2014-11-213-0/+157
* x86: ivybridge: Check BIST value on bootSimon Glass2014-11-211-0/+16
* x86: ivybridge: Perform initial CPU setupSimon Glass2014-11-211-0/+130
* x86: ivybridge: Add early LPC init so that serial worksSimon Glass2014-11-213-0/+61
* x86: ivybridge: Enable PCI in early initSimon Glass2014-11-213-0/+67
* x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass2014-11-212-2/+162
* x86: Add chromebook_link boardSimon Glass2014-11-215-0/+262
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