summaryrefslogtreecommitdiffstats
path: root/arch/x86/cpu/coreboot
Commit message (Expand)AuthorAgeFilesLines
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-247-106/+7
* x86: Add coreboot timestampsSimon Glass2013-05-131-0/+3
* x86: Support adding coreboot timestanps to bootstageSimon Glass2013-05-131-0/+38
* x86: Add TSC timerSimon Glass2013-05-131-1/+3
* x86: Implement panic output for corebootSimon Glass2013-05-131-0/+10
* x86: Fix DRAM bank size init with generic boardSimon Glass2013-04-151-1/+6
* x86: Use sections header to obtain link symbolsSimon Glass2013-03-151-0/+1
* x86: Permit bootstage and timer data to be used prior to relocationSimon Glass2013-03-041-9/+6
* x86: Add function to get top of usable ramSimon Glass2013-03-041-14/+4
* x86: drop unused code in coreboot.cStefan Reinauer2012-12-061-7/+0
* x86: Remove coreboot_ from file nameStefan Reinauer2012-12-062-2/+1
* x86: Provide a way to throttle port80 accessesVadim Bendebury2012-12-061-0/+21
* x86: Issue SMI to finalize Coreboot in final stageDuncan Laurie2012-12-061-0/+4
* x86: Fix MTRR clear to detect which MTRR to useDuncan Laurie2012-12-061-4/+15
* x86: Emit port 80 post codes in show_boot_progress()Stefan Reinauer2012-12-061-0/+2
* x86: coreboot: Set CONFIG_ARCH_DEVICE_TREE correctlyGabe Black2012-12-061-0/+23
* x86: Override calculate_relocation_address to use the e820 mapGabe Black2012-12-061-6/+55
* x86: Ignore memory >4GB when parsing Coreboot tablesDuncan Laurie2012-12-061-0/+4
* x86: Clean up MTRR 7 right before jumping to the kernelStefan Reinauer2012-12-061-0/+18
* x86: Fill in the dram info using the e820 map on coreboot/x86Gabe Black2012-12-061-0/+15
* x86: Enable coreboot timestamp facility support in u-boot.Vadim Bendebury2012-12-063-0/+66
* x86: coreboot: Decode additional coreboot sysinfo tagsSimon Glass2012-11-301-22/+87
* x86: coreboot: Drop sysinfo.cStefan Reinauer2012-11-303-40/+8
* x86: coreboot: Implement recursively scanning PCI bussesGabe Black2012-11-281-3/+23
* x86: coreboot: Tell u-boot about PCI bus 0 when initializingGabe Black2012-11-281-0/+15
* x86: coreboot: Move non-board specific files to coreboot arch directoryStefan Reinauer2012-11-283-0/+119
* x86: Add infrastructure to extract an e820 table from the coreboot tablesGabe Black2011-12-191-1/+37
* x86: Import code from coreboot's libpayload to parse the coreboot tableGabe Black2011-12-194-0/+279
* x86: Initial commit for running as a coreboot payloadGabe Black2011-12-194-0/+148
OpenPOWER on IntegriCloud