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* ARM: socfpga: move SoC sources to mach-socfpgaMasahiro Yamada2015-05-071-289/+0
| | | | | | Our recent trend is to collect SoC files into arch/arm/mach-(SOC). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Kconfig: Move CONFIG_DESIGNWARE_ETH to KconfigSimon Glass2015-04-181-1/+1
| | | | | | | | | | Move this to Kconfig and clean up board config files that use it. Also rename it to CONFIG_ETH_DESIGNWARE to fit with the naming that exists in drivers/net/Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org> Version 1: Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* arm: socfpga: Change watchdog timeoutStefan Roese2014-12-211-1/+11
| | | | | | | | | | | | | | | | The current current watchdog timeout of 12 seconds is a bit small for booting into Linux, especially when using a NFS based rootfs. So lets change this timeout to a more defensive value of 30 seconds. Also we now call the hw_watchdog_init() function so that we override the value already configured from the Preloader. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
* arm: socfpga: Add socfpga_spim_enable() to reset_manager.cStefan Roese2014-11-071-0/+6
| | | | | | | | | | | | | | | | | This function will be needed by the upcoming Designware master SPI driver. As the SPI master controller is held in reset by the current Preloader implementation. So we need to release the reset for the driver to communicate with the controller. This function is called from arch_early_init_r() if the SPI driver is enabled. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
* arm: socfpga: Move code from misc_init_r() to arch_early_init_r()Marek Vasut2014-10-271-1/+1
| | | | | | | | | | | | | Move this initialization code to proper place. The misc_init_r() function is called way too late and the platform initialization code should be executed much earlier. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: Add command to control HPS-FPGA bridgesMarek Vasut2014-10-061-0/+75
| | | | | | | | | | | | | | | | | | Add command to enable and disable the bridges between HPS and FPGA. This patch does have a checkpatch issue with the assembler portion, checkpatch correctly complains that there should be no whitespace before quoted newline. I do not agree that fixing this specific checkpatch issue will improve the readability, thus this one is not addressed. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de>
* arm: socfpga: Move cache_enable to CPU codeMarek Vasut2014-10-061-0/+10
| | | | | | | | | | | | | | | | Move icache_enable() and dcache_enable() function calls from board code into the CPU code and into the enable_caches() function. This is how the cache enabling code was designed to work. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: nic301: Add NIC-301 configuration codePavel Machek2014-10-061-0/+26
| | | | | | | | | | | | | | Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA . The code sets the access permissions for the CPU to the AMBA slaves such that the CPU can access them in both secure and non-secure mode. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
* arm: socfpga: pl310: Map SDRAM to 0x0Marek Vasut2014-10-061-0/+14
| | | | | | | | | | | | | | | Configure the PL310 address filter to make sure DRAM is mapped to 0x0. This code also configures the "remap" register of NIC-301 and sets the required 'mpuzero' bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: fpga: Add SoCFPGA FPGA programming interfacePavel Machek2014-10-061-0/+36
| | | | | | | | | | | | | | | | | | | Add code necessary to program the FPGA part of SoCFPGA from U-Boot with an RBF blob. This patch also integrates the code into the FPGA driver framework in U-Boot so it can be used via the 'fpga' command. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move the not-CPU specific stuff into drivers/fpga/ and base this on the cleaned up altera FPGA support.
* arm: socfpga: misc: Align print_cpuinfo() outputPavel Machek2014-10-061-1/+1
| | | | | | | | | | | | | | Cosmetic change to the print_cpuinfo() function output. Align the output with the rest of initial output produced by U-Boot. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
* arm: socfpga: misc: Add SD controller initPavel Machek2014-10-061-0/+13
| | | | | | | | | | | | | | Add CPU function to register and initialize the dw_mmc SD controller. This allows us to use the HPS SDMMC block. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
* arm: socfpga: misc: Add proper ethernet initializationPavel Machek2014-10-061-15/+43
| | | | | | | | | | | | | | | | | | | | | Add function to initialize the EMAC blocks upon board startup. The preprocessor guards against building on SoCFPGA-VT and against SPL build are not needed as those are handled implicitly via both SPL framework and the socfpga_cyclone5.h config file, which will not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
* arm: socfpga: Add watchdog disable for socfpgaPavel Machek2014-10-061-0/+14
| | | | | | | | | | | | | | | | This adds watchdog disable. It is neccessary for running Linux kernel. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)
* socfpga: initialize designware ethernetPavel Machek2014-08-301-0/+17
| | | | | | | | Enable initialization fo designware ethernet controller. With this patch, ethernet works in my configuration, provided I set ethernet address in the environment. Signed-off-by: Pavel Machek <pavel@denx.de>
* socfpga: Relocate arch common functions away from boardChin Liang See2014-07-051-0/+24
| | | | | | | | | | | | | To move the arch common function away from board folder to arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication for other non Altera dev kit which is using socfpga device. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Detlev Zundel <dzu@denx.de>
* socfpga: Creating driver for Reset ManagerChin Liang See2013-09-061-27/+0
| | | | | | | | | | | | | | Consolidating reset code into reset_manager.c. Also separating reset configuration for virtual target and real hardware Cyclone V development kit Signed-off-by: Chin Liang See <clsee@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-12/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* ARM: Add Altera SOCFPGA Cyclone5Dinh Nguyen2012-10-041-0/+54
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Tom Trini <trini@ti.com> Cc: Wolfgang Denx <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> ---- v8: Remove no_return attribute for reset_cpu Based on v2012.10-rc2
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