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* ARM: OMAP4: fix DDR timings for OMAP4430 ES2.0Janne Grunau2014-02-211-0/+18
| | | | | | | DDR timings were broken since 47abc3df701d8bc26f311350aa523fc1d0f8ad4e for PandaBoard EA1. Signed-off-by: Janne Grunau <j@jannau.net>
* kbuild: change out-of-tree buildMasahiro Yamada2014-02-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit changes the working directory where the build process occurs. Before this commit, build process occurred under the source tree for both in-tree and out-of-tree build. That's why we needed to add $(obj) prefix to all generated files in makefiles like follows: $(obj)u-boot.bin: $(obj)u-boot Here, $(obj) is empty for in-tree build, whereas it points to the output directory for out-of-tree build. And our old build system changes the current working directory with "make -C <sub-dir>" syntax when descending into the sub-directories. On the other hand, Kbuild uses a different idea to handle out-of-tree build and directory descending. The build process of Kbuild always occurs under the output tree. When "O=dir/to/store/output/files" is given, the build system changes the current working directory to that directory and restarts the make. Kbuild uses "make -f $(srctree)/scripts/Makefile.build obj=<sub-dir>" syntax for descending into sub-directories. (We can write it like "make $(obj)=<sub-dir>" with a shorthand.) This means the current working directory is always the top of the output directory. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Gerhard Sittig <gsi@denx.de>
* ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALLJassi Brar2014-01-241-85/+0
| | | | | | | | | The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* pandaboard: 1/1] ARM:OMAP4+: panda-es: Support Rev B3 Elpida DDR2 RAMHardik Patel2013-12-041-2/+2
| | | | Signed-off-by: Hardik Patel <hardik.patel@volansystech.com>
* ARM: DRA7/OMAP5: EMIF: Add workaround for bug 0039SRICHARAN R2013-12-041-0/+5
| | | | | | | | | | | When core power domain hits oswr, then DDR3 memories does not come back while resuming. This is because when EMIF registers are lost, then the controller takes care of copying the values from the shadow registers. If the shadow registers are not updated with the right values, then this results in incorrect settings while resuming. So updating the shadow registers with the corresponding status registers here during the boot. Signed-off-by: Sricharan R <r.sricharan@ti.com>
* ARM: OMAP4: Fix bug in omap4470_volts structLubomir Popov2013-12-041-4/+8
| | | | | | | | | | The struct incorrectly referenced SMPS1 for all three power domains. Fixed this by using SMPS2 and SMPS5 as appropriate. Add some comments and choose voltage values that correspond to voltage selection codes. Signed-off-by: Lubomir Popov <l-popov@ti.com>
* armv7: convert makefiles to Kbuild styleMasahiro Yamada2013-10-311-26/+5
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: omap4: Update sdram setting for panda rev A6Dan Murphy2013-10-141-0/+4
| | | | | | | | | | OMAP4 panda rev A6 is a 4430 es2.3 IC with an updated memory part. The panda rev A6 uses Elpida 2x4Gb memory and no longer uses Micron so the timings needs to be updated Signed-off-by: Dan Murphy <dmurphy@ti.com>
* ARM: OMAP4470: Add Elpida EDB8164B3PF memory configurationLubomir Popov2013-08-281-7/+34
| | | | | | | | | | | | | | OMAP4470 SDP SoM has EDB8164B3PF PoP memory on board. This memory has 4Gb x 2CS = 8Gb configuration. Add configuration for runtime calculation and precalculated cases. Patch is based on a draft Lubomir's patch [1]. [1] http://lists.denx.de/pipermail/u-boot/2013-April/150851.html Signed-off-by: Lubomir Popov <lpopov@mm-sol.com> [taras@ti.com: cleaned up patch and fixed precalculated values] Signed-off-by: Taras Kondratiuk <taras@ti.com>
* ARM: OMAP4470: Add voltage and dpll dataTaras Kondratiuk2013-08-281-0/+36
| | | | | | | | | | | | | OMAP4470 reference design uses TWL6032 PMIC with a following connection scheme: VDD_CORE = TWL6032 SMPS2 VDD_MPU = TWL6032 SMPS1 VDD_IVA = TWL6032 SMPS5 Set voltage and frequency values according to OMAP4470 Data Manual Operating Condition Addendum v0.7 Signed-off-by: Taras Kondratiuk <taras@ti.com>
* ARM: OMAP4470: Add OMAP4470 identificationTaras Kondratiuk2013-08-281-0/+3
| | | | Signed-off-by: Taras Kondratiuk <taras@ti.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-247-118/+7
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: pmic: Make generic bus init and write functionsLokesh Vutla2013-06-101-1/+10
| | | | | | | | | | Voltage scaling can be done in two ways: -> Using SR I2C -> Using GP I2C In order to support both, have a function pointer in pmic_data so that we can call as per our requirement. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.hLokesh Vutla2013-06-101-1/+1
| | | | | | | To be consistent with other ARM platforms, renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: OMAP4+: Cleanup header filesLokesh Vutla2013-06-101-0/+3
| | | | | | | After having the u-boot clean up series, there are many definitions that are unused in header files. Removing all those unused ones. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines commonSRICHARAN R2013-05-103-4/+5
| | | | | | | | These defines are same across OMAP4/5. So move them to omap_common.h. This is required for the patches that follow. Signed-off-by: Sricharan R <r.sricharan@ti.com>
* OMAP4: Fix bug in omap4460_volts structLubomir Popov2013-04-101-4/+4
| | | | | | | | | | | The omap4460_volts struct was incorrectly referencing tps62361 instead of twl6030 as PMIC for the core and mm voltages (the tps is used for mpu supply only). This shall lead to bad OPP settings while booting kernel. Fixing it. Fix some comments as well. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
* arm: omap4: Fix SDRAM AUTO DETECTIONLokesh Vutla2013-04-081-1/+0
| | | | | | | | | | | | | | Commit "8602114 omap: emif: configure emif only when required" breaks SDRAM_AUTO_DETECTION. The issue is dmm_init() depends on emif_sizes[](SDRAM Auto detection) done in do_sdram_init(). The above commit moves dmm_init() above do_sdram_init() because of which dmm_init() uses uninitialized emif_sizes[]. So instead of using global emif_sizes[], get sdram details locally and calculate emif sizes. Reported-by: Michael Cashwell <mboards@prograde.net> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* arm: dra7xx: Add DDR related data for DRA752 ES1.0Lokesh Vutla2013-03-111-3/+15
| | | | | | | | | | DRA752 uses DDR3. Populating the corresponding structures with DDR3 data. Writing into MA registers if only MA is present in that soc. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: dra7xx: clock: Add the dplls dataLokesh Vutla2013-03-111-3/+6
| | | | | | | | | | | | A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is introduced in DRA7xx socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: dra7xx: clock: Add the prcm changesLokesh Vutla2013-03-112-2/+2
| | | | | | | | PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX. So adding the necessary register changes for DRA7XX socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendumSRICHARAN R2013-03-111-76/+88
| | | | | | | | | | | | | | | | | Change OPP settings as per the latest 0.5 version of addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched here to add dummy dividers. While here correcting OPP_NOM mpu, core frequency for OMAP4430 ES2.x Note that OMAP5430 ES1.0 support is still kept alive and would be removed in a cleanup later. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Nishanth Menon <nm@ti.com>
* ARM: OMAP4+: Make control module register structure genericLokesh Vutla2013-03-113-20/+39
| | | | | | | | | | | | A seperate omap_sys_ctrl_regs structure is defined for omap4 & 5. If there is any change in control module for any of the ES versions, a new structure needs to be created. In order to remove this dependency, making the register structure generic for all the omap4+ boards. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Cleanup emif specific filesLokesh Vutla2013-03-111-3/+13
| | | | | | | | | | | | Removing the duplicated code in ddr3 initialization. Also creating structure for lpddr2 mode registers to avoid unnessecary revision checks. These change reduces code addition for future Socs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Clean up the pmic codeSRICHARAN R2013-03-113-124/+70
| | | | | | | | | | The pmic code is duplicated for OMAP 4 and 5. Instead move the data to Soc specific place and share the code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Cleanup the clocks layerSRICHARAN R2013-03-112-394/+366
| | | | | | | | | | | | | | | Currently there is quite a lot of code which is duplicated in the clocks code for OMAP 4 and 5 Socs. Avoiding this here by moving the clocks data to a SOC specific place and the sharing the common code. This helps in addition of a new Soc with minimal changes. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Change the PRCM structure prototype common for all SocsSRICHARAN R2013-03-114-100/+434
| | | | | | | | | | | | The current PRCM structure prototype directly matches the hardware register layout. So there is a need to change this for every new silicon revision which has register space changes. Avoiding this by making the prototye generic and populating the register addresses seperately for all Socs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* omap4: Add comments on some "#endif"s for readability.Robert P. J. Day2012-12-102-3/+3
| | | | | | No functional changes, simply for readability. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* ARM: OMAP4/5: Move USB clocks to essential group.SRICHARAN R2012-07-071-6/+4
| | | | | | | | | USB clocks will be required for fastboot, tftp related functionalities. Move these clocks to essential group inorder to have the functionality working when non-essential clocks are not enabled. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP4/5: Move gpmc clocks to essential group.SRICHARAN R2012-07-071-1/+1
| | | | | | | | | | GPMC clocks are currently getting enabled as a part non-essential clocks. This will be required during NOR boot. Move this to essential group to keep the functionality, when non-essential clocks are not enabled. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP4+: Move external phy initialisations to arch specific place.SRICHARAN R2012-07-071-1/+0
| | | | | | | | | | The external phy is present in the case OMAP5 soc is currently configured in emif-common.c. This results in having dummy structures for those Socs which do not have a external phy. So by having a weak function in emif-common and overriding it in OMAP5, avoids the use of dummy structures. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* omap4: Use a smaller M,N couple for IVA DPLLSebastien Jan2012-07-071-1/+1
| | | | | | | | | | This reduced M,N couple corresponds to the advised value from TI HW team. Tested on 4460 Pandaboard, it also provides peripheral clocks closer to the advised values. Signed-off-by: Sebastien Jan <s-jan@ti.com>
* OMAP5: EMIF: Add support for DDR3 deviceLokesh Vutla2012-07-071-0/+5
| | | | | | | | | In OMAP5432 EMIF controlller supports DDR3 device. This patch adds support for ddr3 device intialization and configuration. Initialization sequence is done as specified in JEDEC specs. This also adds support for ddr3 leveling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: ADD precalculated timings for ddr3Lokesh Vutla2012-07-071-0/+1
| | | | | | | Adding precalculated timings for ddr3 with 1cs adding required registers for ddr3 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* omap4: do not enable auxiliary coresTero Kristo2012-05-151-4/+0
| | | | | | | | | Booting up these cores (dsp / ivahd / cortex-m3) is bad without firmware running on them, and they will hang preventing any kind of sleep transitions later on with the kernel. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: R Sricharan <r.sricharan@ti.com>
* omap4: do not enable fs-usb moduleTero Kristo2012-05-151-2/+0
| | | | | | | If this is done in the bootloader, the FS-USB will later be stuck into intransition state, which will prevent the device from entering idle. Signed-off-by: Tero Kristo <t-kristo@ti.com>
* Add abs() macro to return absolute valueSimon Glass2012-05-151-2/+0
| | | | | | | | | This macro is generally useful to make it available in common. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Tom Rini <trini@ti.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* OMAP4/5: Make the sysctrl structure commonSRICHARAN R2012-05-151-2/+2
| | | | | | | | | Make the sysctrl structure common, so that it can be used in generic functions across socs. Also change the base address of the system control module, to include all the registers and not simply the io regs. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP4/5: Make the silicon revision variable common.SRICHARAN R2012-05-151-10/+10
| | | | | | | | The different silicon revision variable names was defined for OMAP4 and OMAP5 socs. Making the variable common so that some code can be made generic. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: palmas: Configure nominal opp vdd valuesSRICHARAN R2012-05-151-0/+15
| | | | | | | | | | | The nominal opp vdd values as recommended for ES1.0 silicon is set for mpu, core, mm domains using palmas. Also used the right sequence to enable the vcores as per a previous patch from Nishant Menon, which can be dropped now. http://lists.denx.de/pipermail/u-boot/2012-March/119151.html Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon.SRICHARAN R2012-05-151-0/+4
| | | | | | | | | The OMAP5 silicon has new DDR PHY design, which includes a external PHY as well. So configuring the ext PHY parameters here. Also the EMIF timimg registers and a couple of DDR mode registers needs to be updated based on the testing from the actual silicon. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP4: scale voltage of core before MPU scalesNishanth Menon2012-05-151-28/+35
| | | | | | | | | | | | | | | | OMAP4 requires that parent domains scale ahead of dependent domains. This is due to the restrictions in timing closure. To ensure a consistent behavior across all OMAP4 SoC, ensure that vdd_core scale first, then vdd_mpu and finally vdd_iva. As part of doing this refactor the logic to allow for future addition of OMAP4470 without much ado. OMAP4470 uses different SMPS addresses and cannot be introduced in the current code without major rewrite. Reported-by: Isabelle Gros <i-gros@ti.com> Reported-by: Jerome Angeloni <j-angeloni@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP4460: TPS Ensure SET1 is selected after voltage configurationNishanth Menon2012-05-151-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms. Currently we control this pin with a mux configuration as part of boot sequence. Current configuration results in the following voltage waveform: |---------------| (SET1 default 1.4V) | --------(programmed voltage) | <- (This switch happens on mux7,pullup) vdd_mpu(TPS) -----/ (OPP boot voltage) --------- (programmed voltage) vdd_core(TWL6030) -----------------------/ (OPP boot voltage) Problem 1) |<----- Tx ------>| timing violation for a duration Tx close to few milliseconds. Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP. By using GPIO as recommended as standard procedure by TI, the sequence changes to: -------- (programmed voltage) vdd_mpu(TPS) ------------/ (Opp boot voltage) --------- (programmed voltage) vdd_core(TWL6030) -------------/ (OPP boot voltage) NOTE: This does not attempt to address OMAP5 - Aneesh please confirm Reported-by: Isabelle Gros <i-gros@ti.com> Reported-by: Jerome Angeloni <j-angeloni@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP3+: Introduce generic logic for OMAP voltage controllerNishanth Menon2012-05-151-1/+1
| | | | | | | | | | | | | | | | | | | | OMAP Voltage controller is used to generically talk to PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code in multiple SoC code, introduce a common voltage controller logic which can be re-used from elsewhere. With this change, we replace setup_sri2c with omap_vc_init which has the same functionality, and replace the voltage scale replication in do_scale_vcore and do_scale_tps62361 with omap_vc_bypass_send_value. omap_vc_bypass_send_value can also now be used with any configuration of PMIC. NOTE: Voltage controller controlling I2C_SR is a write-only data path, so no register read operation can be implemented. Reported-by: Isabelle Gros <i-gros@ti.com> Reported-by: Jerome Angeloni <j-angeloni@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP4460: Reduce MPU clock speed from 920 to 700Aneesh V2012-02-121-11/+11
| | | | | | | | | | We do not have thermal management or Smartreflex enabled at U-Boot level. So, it's better to stick to OPP100 for MPU instead of the OPP Turbo that is used now. Adjust the VDD_MPU accordingly. Tested-by: Sebastien Jan <s-jan@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com>
* OMAP3+: Clock: Adding ehci clock enablingGovindraj.R2012-02-121-0/+5
| | | | | | | | | | Adding ehci clock enabling mechanism part of clock framework. When essential clocks are enabled during init phase usb host clocks can also be enabled from clock framework. Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Tested-by: Stefano Babic <sbabic@denx.de>
* omap4: fix boot issue on ES2.0 PandaAneesh V2012-01-161-2/+2
| | | | | | | | | | | | | Fix boot issue on ES2.0 Panda by tuning some IO settings. The CONTROL_EFUSE_2 register has to be over-ridden in software for 4430 boards. Commit 23e9f0723e48615332119de4f4ec7a833a282628 wrongly did this for CONTROL_EFUSE_1. Reverting this and doing it for CONTROL_EFUSE_2. Signed-off-by: Aneesh V <aneesh@ti.com> Tested-by: Raúl Porcel <armin76@gentoo.org>
* omap4: fix IO settingAneesh V2011-12-061-1/+6
| | | | | | | | | | | | The value from TRIM is not working for some 4430 silicons. So, override with hw team recommended value. However, for 4460 TRIM value shall be used as long as the part is trimmed This fixes boot problem on some OMAP4430 ES2.0 Panda boards out there. Cc: Steve Sakoman <sakoman@gmail.com> Signed-off-by: Aneesh V <aneesh@ti.com>
* omap4460: add ES1.1 identificationAneesh V2011-12-061-1/+9
| | | | Signed-off-by: Aneesh V <aneesh@ti.com>
* omap4/5: Add support for booting with CH.Sricharan2011-11-151-12/+32
| | | | | | | | | | | | | | | | Configuration header(CH) is 512 byte header attached to an OMAP boot image that will help ROM code to initialize clocks, SDRAM etc and copy U-Boot directly into SDRAM. CH can help us in by-passing SPL and directly boot U-boot, hence it's an alternative for SPL. However, we intend to support both CH and SPL for OMAP4/5. Initialization done through CH is limited and is not equivalent to that done by SPL. So U-Boot has to distinguish between the two cases and handle them accordingly. This patch takes care of doing this. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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