diff options
Diffstat (limited to 'include')
47 files changed, 686 insertions, 46 deletions
diff --git a/include/common_timing_params.h b/include/common_timing_params.h new file mode 100644 index 0000000000..76338d4e6c --- /dev/null +++ b/include/common_timing_params.h @@ -0,0 +1,57 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#ifndef COMMON_TIMING_PARAMS_H +#define COMMON_TIMING_PARAMS_H + +typedef struct { + /* parameters to constrict */ + + unsigned int tckmin_x_ps; + unsigned int tckmax_ps; + unsigned int tckmax_max_ps; + unsigned int trcd_ps; + unsigned int trp_ps; + unsigned int tras_ps; + + unsigned int twr_ps; /* maximum = 63750 ps */ + unsigned int twtr_ps; /* maximum = 63750 ps */ + unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns + = 511750 ps */ + + unsigned int trrd_ps; /* maximum = 63750 ps */ + unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ + + unsigned int refresh_rate_ps; + unsigned int extended_op_srt; + + unsigned int tis_ps; /* byte 32, spd->ca_setup */ + unsigned int tih_ps; /* byte 33, spd->ca_hold */ + unsigned int tds_ps; /* byte 34, spd->data_setup */ + unsigned int tdh_ps; /* byte 35, spd->data_hold */ + unsigned int trtp_ps; /* byte 38, spd->trtp */ + unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ + unsigned int tqhs_ps; /* byte 45, spd->tqhs */ + + unsigned int ndimms_present; + unsigned int lowest_common_SPD_caslat; + unsigned int highest_common_derated_caslat; + unsigned int additive_latency; + unsigned int all_dimms_burst_lengths_bitmask; + unsigned int all_dimms_registered; + unsigned int all_dimms_unbuffered; + unsigned int all_dimms_ecc_capable; + + unsigned long long total_mem; + unsigned long long base_address; + + /* DDR3 RDIMM */ + unsigned char rcw[16]; /* Register Control Word 0-15 */ +} common_timing_params_t; + +#endif diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 268f66ec0e..b2a5c19e0e 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -193,7 +193,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DDR_SPD #define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 036f264c97..499d8c2054 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -80,7 +80,7 @@ #define CONFIG_SYS_MEMTEST_END 0x01ffffff /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #undef CONFIG_SYS_DDR_RAW_TIMING #undef CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 75889b3574..a6601fee86 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -134,7 +134,7 @@ #define CONFIG_SYS_MEMTEST_END 0x01ffffff /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 08156c531d..f173b07b4d 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -103,7 +103,7 @@ #define CONFIG_PANIC_HANG /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x50 diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h index f3f2136668..bbfee7d308 100644 --- a/include/configs/HWW1U1A.h +++ b/include/configs/HWW1U1A.h @@ -255,7 +255,7 @@ /* -------------------------------------------------------------------- */ /* FreeScale DDR2/3 SDRAM Controller */ -#define CONFIG_FSL_DDR2 /* Our SDRAM slot is DDR2 */ +#define CONFIG_SYS_FSL_DDR2 /* Our SDRAM slot is DDR2 */ #define CONFIG_DDR_ECC /* Enable ECC by default */ #define CONFIG_DDR_SPD /* Detect DDR config from SPD EEPROM */ #define CONFIG_SPD_EEPROM /* ...why 2 config variables for this? */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 3f742a2bba..a80a6966bf 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -62,11 +62,11 @@ #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ /* - * define CONFIG_FSL_DDR2 to use unified DDR driver + * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver * undefine it to use old spd_sdram.c */ -#define CONFIG_FSL_DDR2 -#ifdef CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 +#ifdef CONFIG_SYS_FSL_DDR2 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x52 #define SPD_EEPROM_ADDRESS2 0x51 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 8197f89e4e..9ab1bc106b 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -122,7 +122,7 @@ /* DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 66893688e6..046b14bdda 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -78,7 +78,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index e24c597453..eca3b537b4 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -51,7 +51,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 2e76df681b..8132ec055b 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -63,7 +63,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 9ff048af6d..6acd54db85 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -75,7 +75,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 7f0f927ea1..5ffdd01629 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -51,7 +51,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index b7c4a60309..bb9ae2dcb5 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -75,7 +75,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index c9a15395c3..7406ac3be8 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -60,7 +60,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 341f6a89b4..df5572b3a8 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -98,7 +98,7 @@ extern unsigned long get_clock_freq(void); #endif /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index c7511449ea..afb195fe4e 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -106,7 +106,7 @@ /* DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 97f5c877e1..41ebe31dd4 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -92,7 +92,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 8ed5050766..0e666bac01 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -108,7 +108,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 50c365a5b1..eab386add4 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -178,7 +178,7 @@ #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 1470526d0b..262c3e5f1f 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -177,7 +177,7 @@ /* DDR Setup */ #define CONFIG_DDR_SPD #define CONFIG_VERY_BIG_RAM -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #ifdef CONFIG_DDR_ECC #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index e49523e940..7de6814a03 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -74,7 +74,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_DDR_SPD -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */ #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 282f5c1a12..b592c1966a 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -141,7 +141,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h index 9cc219e5a8..15d2a43cd0 100644 --- a/include/configs/P2020COME.h +++ b/include/configs/P2020COME.h @@ -105,7 +105,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 8a29eaa507..9d3d9b33e5 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -109,9 +109,9 @@ /* DDR Setup */ #define CONFIG_VERY_BIG_RAM #ifdef CONFIG_DDR2 -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #else -#define CONFIG_FSL_DDR3 1 +#define CONFIG_SYS_FSL_DDR3 1 #endif /* ECC will be enabled based on perf_mode environment variable */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 0df6f1a2d9..b238574b5d 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -175,7 +175,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x52 diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 7c6bec8f76..43a5778004 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -170,7 +170,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index 620387fcd0..79312311d8 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -156,7 +156,7 @@ #define CONFIG_DDR_SPD #define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h index 4b023f9e84..eff08e3804 100644 --- a/include/configs/T1042RDB_PI.h +++ b/include/configs/T1042RDB_PI.h @@ -156,7 +156,7 @@ #define CONFIG_DDR_SPD #define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 413f0867f4..46d4f9865f 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -138,7 +138,7 @@ #define CONFIG_SYS_SDRAM_SIZE 1024 #define CONFIG_VERY_BIG_RAM -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 562caa5845..665295c1a2 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -173,7 +173,7 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 2d5320b5cd..7700b38c2d 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -111,7 +111,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h index 6d0d392b77..ec09e15dbf 100644 --- a/include/configs/mpq101.h +++ b/include/configs/mpq101.h @@ -52,7 +52,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 91a678212d..57ed019952 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -325,7 +325,7 @@ #endif /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 76189e136f..9837100e31 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -89,7 +89,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M #define CONFIG_CHIP_SELECTS_PER_CTRL 1 diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 6d970608f2..bdb8eb529d 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -102,7 +102,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #undef CONFIG_DDR_ECC /* only for ECC DDR module */ /* diff --git a/include/configs/socrates.h b/include/configs/socrates.h index b6fbe23706..0e6b86412d 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -80,7 +80,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 9b3f0cc69f..ee1f1f3ed0 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -98,7 +98,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 805814f4fb..63dd767047 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -112,7 +112,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 3f54f1423e..d9b0ed07d6 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -87,7 +87,7 @@ #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE #define CONFIG_DDR_SPD -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 /* diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 4738c23350..88d7f88cc0 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -40,7 +40,7 @@ /* * DDR config */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index 33428803eb..f39d6f9105 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -39,7 +39,7 @@ /* * DDR config */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 9da845d9a2..e1bdf90de4 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -49,7 +49,7 @@ /* * DDR config */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 4137cc9208..2328c7a62e 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -49,7 +49,7 @@ /* * DDR config */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h new file mode 100644 index 0000000000..e03f9db5f2 --- /dev/null +++ b/include/fsl_ddr.h @@ -0,0 +1,105 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#ifndef FSL_DDR_MAIN_H +#define FSL_DDR_MAIN_H + +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> + +#include <common_timing_params.h> + +#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) +/* + * Bind the main DDR setup driver's generic names + * to this specific DDR technology. + */ +static __inline__ int +compute_dimm_parameters(const generic_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) +{ + return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); +} +#endif + +/* + * Data Structures + * + * All data structures have to be on the stack + */ +#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR + +typedef struct { + generic_spd_eeprom_t + spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; + struct dimm_params_s + dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; + memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; + common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; + fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; +} fsl_ddr_info_t; + +/* Compute steps */ +#define STEP_GET_SPD (1 << 0) +#define STEP_COMPUTE_DIMM_PARMS (1 << 1) +#define STEP_COMPUTE_COMMON_PARMS (1 << 2) +#define STEP_GATHER_OPTS (1 << 3) +#define STEP_ASSIGN_ADDRESSES (1 << 4) +#define STEP_COMPUTE_REGS (1 << 5) +#define STEP_PROGRAM_REGS (1 << 6) +#define STEP_ALL 0xFFF + +unsigned long long +fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, + unsigned int size_only); + +const char *step_to_string(unsigned int step); + +unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts, + fsl_ddr_cfg_regs_t *ddr, + const common_timing_params_t *common_dimm, + const dimm_params_t *dimm_parameters, + unsigned int dbw_capacity_adjust, + unsigned int size_only); +unsigned int compute_lowest_common_dimm_parameters( + const dimm_params_t *dimm_params, + common_timing_params_t *outpdimm, + unsigned int number_of_dimms); +unsigned int populate_memctl_options(int all_dimms_registered, + memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num); +void check_interleaving_options(fsl_ddr_info_t *pinfo); + +unsigned int mclk_to_picos(unsigned int mclk); +unsigned int get_memory_clk_period_ps(void); +unsigned int picos_to_mclk(unsigned int picos); +void fsl_ddr_set_lawbar( + const common_timing_params_t *memctl_common_params, + unsigned int memctl_interleaved, + unsigned int ctrl_num); + +int fsl_ddr_interactive_env_var_exists(void); +unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num); + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); + +/* processor specific function */ +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step); + +/* board specific function */ +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number); +#endif diff --git a/include/fsl_ddr_dimm_params.h b/include/fsl_ddr_dimm_params.h new file mode 100644 index 0000000000..99a72bc6e1 --- /dev/null +++ b/include/fsl_ddr_dimm_params.h @@ -0,0 +1,101 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#ifndef DDR2_DIMM_PARAMS_H +#define DDR2_DIMM_PARAMS_H + +#define EDC_DATA_PARITY 1 +#define EDC_ECC 2 +#define EDC_AC_PARITY 4 + +/* Parameters for a DDR2 dimm computed from the SPD */ +typedef struct dimm_params_s { + + /* DIMM organization parameters */ + char mpart[19]; /* guaranteed null terminated */ + + unsigned int n_ranks; + unsigned long long rank_density; + unsigned long long capacity; + unsigned int data_width; + unsigned int primary_sdram_width; + unsigned int ec_sdram_width; + unsigned int registered_dimm; + unsigned int device_width; /* x4, x8, x16 components */ + + /* SDRAM device parameters */ + unsigned int n_row_addr; + unsigned int n_col_addr; + unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ + unsigned int n_banks_per_sdram_device; + unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ + unsigned int row_density; + + /* used in computing base address of DIMMs */ + unsigned long long base_address; + /* mirrored DIMMs */ + unsigned int mirrored_dimm; /* only for ddr3 */ + + /* DIMM timing parameters */ + + unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */ + unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */ + unsigned int taa_ps; /* minimum CAS latency time, only for ddr3 */ + unsigned int tfaw_ps; /* four active window delay, only for ddr3 */ + + /* + * SDRAM clock periods + * The range for these are 1000-10000 so a short should be sufficient + */ + unsigned int tckmin_x_ps; + unsigned int tckmin_x_minus_1_ps; + unsigned int tckmin_x_minus_2_ps; + unsigned int tckmax_ps; + + /* SPD-defined CAS latencies */ + unsigned int caslat_x; + unsigned int caslat_x_minus_1; + unsigned int caslat_x_minus_2; + + unsigned int caslat_lowest_derated; /* Derated CAS latency */ + + /* basic timing parameters */ + unsigned int trcd_ps; + unsigned int trp_ps; + unsigned int tras_ps; + + unsigned int twr_ps; /* maximum = 63750 ps */ + unsigned int twtr_ps; /* maximum = 63750 ps */ + unsigned int trfc_ps; /* max = 255 ns + 256 ns + .75 ns + = 511750 ps */ + + unsigned int trrd_ps; /* maximum = 63750 ps */ + unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ + + unsigned int refresh_rate_ps; + unsigned int extended_op_srt; + + /* DDR3 doesn't need these as below */ + unsigned int tis_ps; /* byte 32, spd->ca_setup */ + unsigned int tih_ps; /* byte 33, spd->ca_hold */ + unsigned int tds_ps; /* byte 34, spd->data_setup */ + unsigned int tdh_ps; /* byte 35, spd->data_hold */ + unsigned int trtp_ps; /* byte 38, spd->trtp */ + unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ + unsigned int tqhs_ps; /* byte 45, spd->tqhs */ + + /* DDR3 RDIMM */ + unsigned char rcw[16]; /* Register Control Word 0-15 */ +} dimm_params_t; + +extern unsigned int ddr_compute_dimm_parameters( + const generic_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number); + +#endif diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h new file mode 100644 index 0000000000..16cccc7708 --- /dev/null +++ b/include/fsl_ddr_sdram.h @@ -0,0 +1,377 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#ifndef FSL_DDR_MEMCTL_H +#define FSL_DDR_MEMCTL_H + +/* + * Pick a basic DDR Technology. + */ +#include <ddr_spd.h> + +#define SDRAM_TYPE_DDR1 2 +#define SDRAM_TYPE_DDR2 3 +#define SDRAM_TYPE_LPDDR1 6 +#define SDRAM_TYPE_DDR3 7 + +#define DDR_BL4 4 /* burst length 4 */ +#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ +#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ +#define DDR_BL8 8 /* burst length 8 */ + +#define DDR3_RTT_OFF 0 +#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ +#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ +#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ +#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ +#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ + +#define DDR2_RTT_OFF 0 +#define DDR2_RTT_75_OHM 1 +#define DDR2_RTT_150_OHM 2 +#define DDR2_RTT_50_OHM 3 + +#if defined(CONFIG_SYS_FSL_DDR1) +#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) +typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1 +#endif +#elif defined(CONFIG_SYS_FSL_DDR2) +#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) +typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 +#endif +#elif defined(CONFIG_SYS_FSL_DDR3) +#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ +typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 +#endif +#endif /* #if defined(CONFIG_SYS_FSL_DDR1) */ + +#define FSL_DDR_ODT_NEVER 0x0 +#define FSL_DDR_ODT_CS 0x1 +#define FSL_DDR_ODT_ALL_OTHER_CS 0x2 +#define FSL_DDR_ODT_OTHER_DIMM 0x3 +#define FSL_DDR_ODT_ALL 0x4 +#define FSL_DDR_ODT_SAME_DIMM 0x5 +#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6 +#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 + +/* define bank(chip select) interleaving mode */ +#define FSL_DDR_CS0_CS1 0x40 +#define FSL_DDR_CS2_CS3 0x20 +#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) +#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) + +/* define memory controller interleaving mode */ +#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 +#define FSL_DDR_PAGE_INTERLEAVING 0x1 +#define FSL_DDR_BANK_INTERLEAVING 0x2 +#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 +#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA +#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC +#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD +/* placeholder for 4-way interleaving */ +#define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A +#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C +#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D + +#define SDRAM_CS_CONFIG_EN 0x80000000 + +/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration + */ +#define SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG_SREN 0x40000000 +#define SDRAM_CFG_ECC_EN 0x20000000 +#define SDRAM_CFG_RD_EN 0x10000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 +#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 +#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 +#define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_DBW_MASK 0x00180000 +#define SDRAM_CFG_DBW_SHIFT 19 +#define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_16_BE 0x00100000 +#define SDRAM_CFG_8_BE 0x00040000 +#define SDRAM_CFG_NCAP 0x00020000 +#define SDRAM_CFG_2T_EN 0x00008000 +#define SDRAM_CFG_BI 0x00000001 + +#define SDRAM_CFG2_D_INIT 0x00000010 +#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 +#define SDRAM_CFG2_ODT_NEVER 0 +#define SDRAM_CFG2_ODT_ONLY_WRITE 1 +#define SDRAM_CFG2_ODT_ONLY_READ 2 +#define SDRAM_CFG2_ODT_ALWAYS 3 + +#define TIMING_CFG_2_CPO_MASK 0x0F800000 + +#if defined(CONFIG_P4080) +#define RD_TO_PRE_MASK 0xf +#define RD_TO_PRE_SHIFT 13 +#define WR_DATA_DELAY_MASK 0xf +#define WR_DATA_DELAY_SHIFT 9 +#else +#define RD_TO_PRE_MASK 0x7 +#define RD_TO_PRE_SHIFT 13 +#define WR_DATA_DELAY_MASK 0x7 +#define WR_DATA_DELAY_SHIFT 10 +#endif + +/* DDR_MD_CNTL */ +#define MD_CNTL_MD_EN 0x80000000 +#define MD_CNTL_CS_SEL_CS0 0x00000000 +#define MD_CNTL_CS_SEL_CS1 0x10000000 +#define MD_CNTL_CS_SEL_CS2 0x20000000 +#define MD_CNTL_CS_SEL_CS3 0x30000000 +#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000 +#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000 +#define MD_CNTL_MD_SEL_MR 0x00000000 +#define MD_CNTL_MD_SEL_EMR 0x01000000 +#define MD_CNTL_MD_SEL_EMR2 0x02000000 +#define MD_CNTL_MD_SEL_EMR3 0x03000000 +#define MD_CNTL_SET_REF 0x00800000 +#define MD_CNTL_SET_PRE 0x00400000 +#define MD_CNTL_CKE_CNTL_LOW 0x00100000 +#define MD_CNTL_CKE_CNTL_HIGH 0x00200000 +#define MD_CNTL_WRCW 0x00080000 +#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) + +/* DDR_CDR1 */ +#define DDR_CDR1_DHC_EN 0x80000000 +#define DDR_CDR1_ODT_SHIFT 17 +#define DDR_CDR1_ODT_MASK 0x6 +#define DDR_CDR2_ODT_MASK 0x1 +#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) +#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) + +#if (defined(CONFIG_SYS_FSL_DDR_VER) && \ + (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) +#define DDR_CDR_ODT_OFF 0x0 +#define DDR_CDR_ODT_120ohm 0x1 +#define DDR_CDR_ODT_180ohm 0x2 +#define DDR_CDR_ODT_75ohm 0x3 +#define DDR_CDR_ODT_110ohm 0x4 +#define DDR_CDR_ODT_60hm 0x5 +#define DDR_CDR_ODT_70ohm 0x6 +#define DDR_CDR_ODT_47ohm 0x7 +#else +#define DDR_CDR_ODT_75ohm 0x0 +#define DDR_CDR_ODT_55ohm 0x1 +#define DDR_CDR_ODT_60ohm 0x2 +#define DDR_CDR_ODT_50ohm 0x3 +#define DDR_CDR_ODT_150ohm 0x4 +#define DDR_CDR_ODT_43ohm 0x5 +#define DDR_CDR_ODT_120ohm 0x6 +#endif + +/* Record of register values computed */ +typedef struct fsl_ddr_cfg_regs_s { + struct { + unsigned int bnds; + unsigned int config; + unsigned int config_2; + } cs[CONFIG_CHIP_SELECTS_PER_CTRL]; + unsigned int timing_cfg_3; + unsigned int timing_cfg_0; + unsigned int timing_cfg_1; + unsigned int timing_cfg_2; + unsigned int ddr_sdram_cfg; + unsigned int ddr_sdram_cfg_2; + unsigned int ddr_sdram_mode; + unsigned int ddr_sdram_mode_2; + unsigned int ddr_sdram_mode_3; + unsigned int ddr_sdram_mode_4; + unsigned int ddr_sdram_mode_5; + unsigned int ddr_sdram_mode_6; + unsigned int ddr_sdram_mode_7; + unsigned int ddr_sdram_mode_8; + unsigned int ddr_sdram_md_cntl; + unsigned int ddr_sdram_interval; + unsigned int ddr_data_init; + unsigned int ddr_sdram_clk_cntl; + unsigned int ddr_init_addr; + unsigned int ddr_init_ext_addr; + unsigned int timing_cfg_4; + unsigned int timing_cfg_5; + unsigned int ddr_zq_cntl; + unsigned int ddr_wrlvl_cntl; + unsigned int ddr_wrlvl_cntl_2; + unsigned int ddr_wrlvl_cntl_3; + unsigned int ddr_sr_cntr; + unsigned int ddr_sdram_rcw_1; + unsigned int ddr_sdram_rcw_2; + unsigned int ddr_eor; + unsigned int ddr_cdr1; + unsigned int ddr_cdr2; + unsigned int err_disable; + unsigned int err_int_en; + unsigned int debug[32]; +} fsl_ddr_cfg_regs_t; + +typedef struct memctl_options_partial_s { + unsigned int all_dimms_ecc_capable; + unsigned int all_dimms_tckmax_ps; + unsigned int all_dimms_burst_lengths_bitmask; + unsigned int all_dimms_registered; + unsigned int all_dimms_unbuffered; + /* unsigned int lowest_common_SPD_caslat; */ + unsigned int all_dimms_minimum_trcd_ps; +} memctl_options_partial_t; + +#define DDR_DATA_BUS_WIDTH_64 0 +#define DDR_DATA_BUS_WIDTH_32 1 +#define DDR_DATA_BUS_WIDTH_16 2 +/* + * Generalized parameters for memory controller configuration, + * might be a little specific to the FSL memory controller + */ +typedef struct memctl_options_s { + /* + * Memory organization parameters + * + * if DIMM is present in the system + * where DIMMs are with respect to chip select + * where chip selects are with respect to memory boundaries + */ + unsigned int registered_dimm_en; /* use registered DIMM support */ + + /* Options local to a Chip Select */ + struct cs_local_opts_s { + unsigned int auto_precharge; + unsigned int odt_rd_cfg; + unsigned int odt_wr_cfg; + unsigned int odt_rtt_norm; + unsigned int odt_rtt_wr; + } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; + + /* Special configurations for chip select */ + unsigned int memctl_interleaving; + unsigned int memctl_interleaving_mode; + unsigned int ba_intlv_ctl; + unsigned int addr_hash; + + /* Operational mode parameters */ + unsigned int ecc_mode; /* Use ECC? */ + /* Initialize ECC using memory controller? */ + unsigned int ecc_init_using_memctl; + unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ + /* SREN - self-refresh during sleep */ + unsigned int self_refresh_in_sleep; + unsigned int dynamic_power; /* DYN_PWR */ + /* memory data width to use (16-bit, 32-bit, 64-bit) */ + unsigned int data_bus_width; + unsigned int burst_length; /* BL4, OTF and BL8 */ + /* On-The-Fly Burst Chop enable */ + unsigned int otf_burst_chop_en; + /* mirrior DIMMs for DDR3 */ + unsigned int mirrored_dimm; + unsigned int quad_rank_present; + unsigned int ap_en; /* address parity enable for RDIMM */ + unsigned int x4_en; /* enable x4 devices */ + + /* Global Timing Parameters */ + unsigned int cas_latency_override; + unsigned int cas_latency_override_value; + unsigned int use_derated_caslat; + unsigned int additive_latency_override; + unsigned int additive_latency_override_value; + + unsigned int clk_adjust; /* */ + unsigned int cpo_override; + unsigned int write_data_delay; /* DQS adjust */ + + unsigned int wrlvl_override; + unsigned int wrlvl_sample; /* Write leveling */ + unsigned int wrlvl_start; + unsigned int wrlvl_ctl_2; + unsigned int wrlvl_ctl_3; + + unsigned int half_strength_driver_enable; + unsigned int twot_en; + unsigned int threet_en; + unsigned int bstopre; + unsigned int tcke_clock_pulse_width_ps; /* tCKE */ + unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */ + + /* Rtt impedance */ + unsigned int rtt_override; /* rtt_override enable */ + unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ + unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ + + /* Automatic self refresh */ + unsigned int auto_self_refresh_en; + unsigned int sr_it; + /* ZQ calibration */ + unsigned int zq_en; + /* Write leveling */ + unsigned int wrlvl_en; + /* RCW override for RDIMM */ + unsigned int rcw_override; + unsigned int rcw_1; + unsigned int rcw_2; + /* control register 1 */ + unsigned int ddr_cdr1; + unsigned int ddr_cdr2; + + unsigned int trwt_override; + unsigned int trwt; /* read-to-write turnaround */ +} memctl_options_t; + +extern phys_size_t fsl_ddr_sdram(void); +extern phys_size_t fsl_ddr_sdram_size(void); +extern int fsl_use_spd(void); +extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step); +u32 fsl_ddr_get_intl3r(void); + +static void __board_assert_mem_reset(void) +{ +} + +static void __board_deassert_mem_reset(void) +{ +} + +void board_assert_mem_reset(void) + __attribute__((weak, alias("__board_assert_mem_reset"))); + +void board_deassert_mem_reset(void) + __attribute__((weak, alias("__board_deassert_mem_reset"))); + +static int __board_need_mem_reset(void) +{ + return 0; +} + +int board_need_mem_reset(void) + __attribute__((weak, alias("__board_need_mem_reset"))); + +/* + * The 85xx boards have a common prototype for fixed_sdram so put the + * declaration here. + */ +#ifdef CONFIG_MPC85xx +extern phys_size_t fixed_sdram(void); +#endif + +#if defined(CONFIG_DDR_ECC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + + +typedef struct fixed_ddr_parm{ + int min_freq; + int max_freq; + fsl_ddr_cfg_regs_t *ddr_settings; +} fixed_ddr_parm_t; +#endif |
