diff options
Diffstat (limited to 'include')
51 files changed, 123 insertions, 121 deletions
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 94c8253e60..5249751830 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -83,7 +83,7 @@ #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 3a733795ae..aaddfca2cd 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -85,7 +85,7 @@ #define CONFIG_PCI /* Enable PCI/PCIE */ #if defined(CONFIG_PCI) -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 4d14c8ba37..1e5b501ab1 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -92,7 +92,7 @@ #define CONFIG_PCI /* Enable PCI/PCIE */ #ifdef CONFIG_PCI -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 8cc7f02391..03f17f9c35 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -51,9 +51,9 @@ #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ -#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ -#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ +#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ +#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 6202dffaa5..26d92daff1 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -25,9 +25,9 @@ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* PCI controller 1 */ -#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ -#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ +#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ +#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index dd07dc4fb5..5de8b19828 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -34,7 +34,7 @@ #define CONFIG_PCI /* enable any pci type devices */ #define CONFIG_PCI1 /* PCI controller 1 */ -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #undef CONFIG_PCI2 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 9144f321e0..8c4e5e21ca 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -40,9 +40,9 @@ #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ -#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ +#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ +#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 88ca4f3048..e7f01d00d1 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -45,7 +45,7 @@ #define CONFIG_SYS_SCRATCH_VA 0xc0000000 #define CONFIG_PCI 1 /* Enable PCI/PCIE*/ -#define CONFIG_PCI1 1 /* PCI controler 1 */ +#define CONFIG_PCI1 1 /* PCI controller 1 */ #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 3569849c52..2f94c8214e 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -46,8 +46,8 @@ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */ -#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */ +#define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */ +#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 5719e86f1b..f398b37f5b 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -176,8 +176,8 @@ #define CONFIG_PCI /* Enable PCI/PCIE */ #if defined(CONFIG_PCI) -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 8b29951c98..7457dfcd48 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -134,9 +134,9 @@ #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ -#define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ +#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index fcbe288472..a10310ec27 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -33,9 +33,9 @@ #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ -#define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */ +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ +#define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index b7a08e0a30..b3fb38c63a 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -52,9 +52,9 @@ #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 12260aaf62..ef2ede49b9 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -577,9 +577,9 @@ unsigned long get_board_ddr_clk(void); * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_PCI_INDIRECT_BRIDGE diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 74274cac57..778c64b3f0 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -563,11 +563,11 @@ unsigned long get_board_ddr_clk(void); * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ #ifdef CONFIG_PPC_T1040 -#define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_PCIE4 /* PCIE controller 4 */ #endif #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 4c1175d426..be4ae712b5 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -65,10 +65,10 @@ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ -#define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ +#define CONFIG_PCIE4 /* PCIE controller 4 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 9a3965fa41..ed3493b684 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -130,10 +130,10 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ -#define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ +#define CONFIG_PCIE4 /* PCIE controller 4 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 85df388b6f..d8c57a833b 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -550,10 +550,10 @@ unsigned long get_board_ddr_clk(void); * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ -#define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ +#define CONFIG_PCIE4 /* PCIE controller 4 */ #define CONFIG_FSL_PCIE_RESET #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 5e2d65975d..b6be46e004 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -500,10 +500,10 @@ unsigned long get_board_ddr_clk(void); * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ -#define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ +#define CONFIG_PCIE4 /* PCIE controller 4 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index a0cce858a1..ab838a8036 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -92,9 +92,9 @@ #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index cd8923d7a5..16935a105a 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -162,12 +162,9 @@ "if test $board_name = A335BONE; then " \ "setenv fdtfile am335x-bone.dtb; fi; " \ "if test $board_name = A335BNLT; then " \ - "if test $board_rev = BBG1; then " \ - "setenv fdtfile am335x-bonegreen.dtb; " \ - "else " \ - "setenv fdtfile am335x-boneblack.dtb; " \ - "fi; " \ - "fi; " \ + "setenv fdtfile am335x-boneblack.dtb; fi; " \ + "if test $board_name = BBG1; then " \ + "setenv fdtfile am335x-bonegreen.dtb; fi; " \ "if test $board_name = A33515BB; then " \ "setenv fdtfile am335x-evm.dtb; fi; " \ "if test $board_name = A335X_SK; then " \ diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h index fb12632923..dfa2d93a90 100644 --- a/include/configs/atngw100mkii.h +++ b/include/configs/atngw100mkii.h @@ -1,7 +1,7 @@ /* * Copyright (C) 2006 Atmel Corporation * - * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com> + * Copyright (C) 2012 Andreas Bießmann <andreas@biessmann.org> * * Configuration settings for the AVR32 Network Gateway * diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 1bb8d93ba0..c60c644393 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -245,7 +245,7 @@ * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 96f17d3e7c..a06bfe05ad 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -67,8 +67,8 @@ #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 4280c9cfb4..660646eb91 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -59,8 +59,8 @@ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ diff --git a/include/configs/duovero.h b/include/configs/duovero.h index d8f48efdd8..98afe27287 100644 --- a/include/configs/duovero.h +++ b/include/configs/duovero.h @@ -22,6 +22,7 @@ #include <configs/ti_omap4_common.h> #undef CONFIG_SPL_OS_BOOT +#undef CONFIG_EFI_PARTITION #undef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 83d9e107fe..ffcc4d2630 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -121,7 +121,7 @@ "initrd_high=0xffffffffffffffff\0" \ BOOTENV -/* Preserve enviroment on sd card */ +/* Preserve environment on sd card */ #define CONFIG_COMMAND_HISTORY #define CONFIG_ENV_SIZE 0x1000 diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 9232ee32a7..028623d1ee 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -45,8 +45,8 @@ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 3796395bd6..f605ca6280 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -528,8 +528,8 @@ unsigned long get_board_ddr_clk(void); /* PCIe */ #define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 3e32128485..32d2acc0cd 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -377,8 +377,8 @@ /* PCIe */ #define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 8e0b472fd7..a3aad1b99d 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -185,10 +185,10 @@ unsigned long long get_qixis_addr(void); #endif /* PCIe */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ -#define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ +#define CONFIG_PCIE4 /* PCIE controller 4 */ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #ifdef CONFIG_LS2080A #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 5da50a5094..9bd891586c 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -19,6 +19,13 @@ #include <configs/ti_omap3_common.h> #include <asm/mach-types.h> +/* SRAM starts at 0x40200000 and ends at 0x4020FFFF (64KB) */ +#undef CONFIG_SPL_MAX_SIZE +#undef CONFIG_SPL_TEXT_BASE + +#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_TEXT_BASE 0x40200000 + /* * Display CPU and Board information */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 055dcb7c61..3c11e2acc2 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -34,7 +34,7 @@ #undef CONFIG_SPL_TEXT_BASE #undef CONFIG_SPL_MAX_SIZE #define CONFIG_SPL_TEXT_BASE 0x40200000 -#define CONFIG_SPL_MAX_SIZE (64 * 1024) +#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE) /* Display CPU and Board information */ @@ -140,7 +140,7 @@ #define CONFIG_PREBOOT \ "echo ======================NOTICE============================;"\ "echo \"The u-boot environment is not set.\";" \ - "echo \"If using a display a valid display varible for your panel\";" \ + "echo \"If using a display a valid display variable for your panel\";" \ "echo \"needs to be set.\";" \ "echo \"Valid display options are:\";" \ "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index c066eae539..fbd0c2a070 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -12,9 +12,9 @@ #include <configs/ti_omap3_common.h> #undef CONFIG_SPL_MAX_SIZE -#define CONFIG_SPL_MAX_SIZE (64*1024) #undef CONFIG_SPL_TEXT_BASE #define CONFIG_SPL_TEXT_BASE 0x40200000 +#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE) #define CONFIG_BCH diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 596193d5c4..71b2fa9c07 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -306,8 +306,8 @@ #define CONFIG_FSL_ELBC #define CONFIG_PCI -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index f2959c9b23..9b75afe92a 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -48,8 +48,8 @@ #define CONFIG_FSL_ELBC #define CONFIG_PCI -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index 1f33bc62e2..816c571511 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -102,7 +102,7 @@ "run mmcboot;" \ "run nandboot;" -/* NS16550 Configuration: primary UART via FDTI */ +/* NS16550 Configuration: primary UART via FTDI */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index f34cef519c..a7c7aef71a 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -44,8 +44,8 @@ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_PCI 1 /* Enable PCIE */ -#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index af61f21693..8ce337e0a7 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -32,9 +32,9 @@ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 2c7d5425ef..7db08813e4 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -219,8 +219,8 @@ #endif /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* address 0x40000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 /* 384 KB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ /* FAT sd card locations. */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 586d84886e..5fad3c1242 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -122,7 +122,10 @@ "loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \ "mmcboot=echo Booting from mmc${mmcdev} ...; " \ "run args_mmc; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ + "if run loadimage; then " \ + "run loadfdt; " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "fi;\0" \ "uimageboot=echo Booting from mmc${mmcdev} ...; " \ "run args_mmc; " \ "bootm ${loadaddr}\0" \ diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index af02efbdef..86c9b4c41f 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -30,8 +30,8 @@ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#define CONFIG_PCIE1 1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 1 /* PCIE controler 2 */ +#define CONFIG_PCIE1 1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 1 /* PCIE controller 2 */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index a1c5826f7b..6a06b0ab1c 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -30,8 +30,8 @@ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#define CONFIG_PCIE1 1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 1 /* PCIE controler 2 */ +#define CONFIG_PCIE1 1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 1 /* PCIE controller 2 */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 02685ca1a8..5b377e35ee 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -31,7 +31,7 @@ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#define CONFIG_PCIE1 1 /* PCIE controler 1 (PEX8112 or XMC) */ +#define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ diff --git a/include/env_flags.h b/include/env_flags.h index 9e87e1b7db..0dcec0689b 100644 --- a/include/env_flags.h +++ b/include/env_flags.h @@ -57,8 +57,8 @@ enum env_flags_varaccess { "gatewayip:i," \ "netmask:i," \ "serverip:i," \ - "nvlan:i," \ - "vlan:i," \ + "nvlan:d," \ + "vlan:d," \ "dnsip:i," #else #define ETHADDR_FLAGS diff --git a/include/fdtdec.h b/include/fdtdec.h index fb88273935..37d482aba7 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -570,7 +570,7 @@ int fdtdec_check_fdt(void); * @param id Compatible ID to look for * @param node_list Place to put list of found nodes * @param maxcount Maximum number of nodes to find - * @return number of nodes found on success, FTD_ERR_... on error + * @return number of nodes found on success, FDT_ERR_... on error */ int fdtdec_find_aliases_for_id(const void *blob, const char *name, enum fdt_compat_id id, int *node_list, int maxcount); diff --git a/include/linux/fb.h b/include/linux/fb.h index 652cf3bab7..fcf331b79f 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -388,14 +388,14 @@ struct fb_cursor_user { #define FB_EVENT_GET_CONSOLE_MAP 0x07 /* CONSOLE-SPECIFIC: set console to framebuffer mapping */ #define FB_EVENT_SET_CONSOLE_MAP 0x08 -/* A hardware display blank change occured */ +/* A hardware display blank change occurred */ #define FB_EVENT_BLANK 0x09 /* Private modelist is to be replaced */ #define FB_EVENT_NEW_MODELIST 0x0A /* The resolution of the passed in fb_info about to change and all vc's should be changed */ #define FB_EVENT_MODE_CHANGE_ALL 0x0B -/* A software display blank change occured */ +/* A software display blank change occurred */ #define FB_EVENT_CONBLANK 0x0C /* Get drawing requirements */ #define FB_EVENT_GET_REQ 0x0D diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h index 6cbae45022..3a75674359 100644 --- a/include/linux/mtd/omap_gpmc.h +++ b/include/linux/mtd/omap_gpmc.h @@ -2,7 +2,7 @@ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com> * Rohit Choraria <rohitkc@ti.com> * - * (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com> + * (C) Copyright 2013 Andreas Bießmann <andreas@biessmann.org> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/include/net.h b/include/net.h index 1fb419424b..05800c4422 100644 --- a/include/net.h +++ b/include/net.h @@ -465,20 +465,14 @@ struct icmp_hdr { #define IP_ICMP_HDR_SIZE (IP_HDR_SIZE + ICMP_HDR_SIZE) /* - * Maximum packet size; used to allocate packet storage. - * TFTP packets can be 524 bytes + IP header + ethernet header. - * Lets be conservative, and go for 38 * 16. (Must also be - * a multiple of 32 bytes). - */ -/* - * AS.HARNOIS : Better to set PKTSIZE to maximum size because - * traffic type is not always controlled - * maximum packet size = 1518 + * Maximum packet size; used to allocate packet storage. Use + * the maxium Ethernet frame size as specified by the Ethernet + * standard including the 802.1Q tag (VLAN tagging). + * maximum packet size = 1522 * maximum packet size and multiple of 32 bytes = 1536 */ -#define PKTSIZE 1518 +#define PKTSIZE 1522 #define PKTSIZE_ALIGN 1536 -/*#define PKTSIZE 608*/ /* * Maximum receive ring size; that is, the number of packets diff --git a/include/test/ut.h b/include/test/ut.h index da7c1a9d26..85434d785a 100644 --- a/include/test/ut.h +++ b/include/test/ut.h @@ -17,9 +17,9 @@ struct unit_test_state; * ut_fail() - Record failure of a unit test * * @uts: Test state - * @fname: Filename where the error occured - * @line: Line number where the error occured - * @func: Function name where the error occured + * @fname: Filename where the error occurred + * @line: Line number where the error occurred + * @func: Function name where the error occurred * @cond: The condition that failed */ void ut_fail(struct unit_test_state *uts, const char *fname, int line, @@ -29,9 +29,9 @@ void ut_fail(struct unit_test_state *uts, const char *fname, int line, * ut_failf() - Record failure of a unit test * * @uts: Test state - * @fname: Filename where the error occured - * @line: Line number where the error occured - * @func: Function name where the error occured + * @fname: Filename where the error occurred + * @line: Line number where the error occurred + * @func: Function name where the error occurred * @cond: The condition that failed * @fmt: printf() format string for the error, followed by args */ diff --git a/include/usbdevice.h b/include/usbdevice.h index da5af6efe4..f27e17f124 100644 --- a/include/usbdevice.h +++ b/include/usbdevice.h @@ -438,7 +438,7 @@ typedef enum usb_device_event { DEVICE_HUB_RESET, /* bi - bus has been unplugged */ DEVICE_DESTROY, /* bi - device instance should be destroyed */ - DEVICE_HOTPLUG, /* bi - a hotplug event has occured */ + DEVICE_HOTPLUG, /* bi - a hotplug event has occurred */ DEVICE_FUNCTION_PRIVATE, /* function - private */ |
