diff options
Diffstat (limited to 'cpu')
49 files changed, 1127 insertions, 1294 deletions
diff --git a/cpu/arm920t/at91rm9200/ether.c b/cpu/arm920t/at91rm9200/ether.c index f20e070343..b00b948ee8 100644 --- a/cpu/arm920t/at91rm9200/ether.c +++ b/cpu/arm920t/at91rm9200/ether.c @@ -155,6 +155,7 @@ int eth_init (bd_t * bd) { int ret; int i; + uchar enetaddr[6]; p_mac = AT91C_BASE_EMAC; @@ -190,9 +191,10 @@ int eth_init (bd_t * bd) rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; rbfp = &rbfdt[0]; - p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16) - | (bd->bi_enetaddr[1] << 8) | (bd->bi_enetaddr[0]); - p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] << 8) | (bd->bi_enetaddr[4]); + eth_getenv_enetaddr("ethaddr", enetaddr); + p_mac->EMAC_SA2L = (enetaddr[3] << 24) | (enetaddr[2] << 16) + | (enetaddr[1] << 8) | (enetaddr[0]); + p_mac->EMAC_SA2H = (enetaddr[5] << 8) | (enetaddr[4]); p_mac->EMAC_RBQP = (long) (&rbfdt[0]); p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA); diff --git a/cpu/arm926ejs/at91/u-boot.lds b/cpu/arm926ejs/at91/u-boot.lds index 4778d1e039..ebb1f93864 100644 --- a/cpu/arm926ejs/at91/u-boot.lds +++ b/cpu/arm926ejs/at91/u-boot.lds @@ -37,7 +37,7 @@ SECTIONS } . = ALIGN(4); - .rodata : { *(.rodata) } + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); .data : { *(.data) } diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c index 28a102091a..b385b912b4 100644 --- a/cpu/arm_cortexa8/omap3/sys_info.c +++ b/cpu/arm_cortexa8/omap3/sys_info.c @@ -36,6 +36,32 @@ static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE; static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE; static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE; +/***************************************************************** + * dieid_num_r(void) - read and set die ID + *****************************************************************/ +void dieid_num_r(void) +{ + ctrl_id_t *id_base = (ctrl_id_t *)OMAP34XX_ID_L4_IO_BASE; + char *uid_s, die_id[34]; + u32 id[4]; + + memset(die_id, 0, sizeof(die_id)); + + uid_s = getenv("dieid#"); + + if (uid_s == NULL) { + id[3] = readl(&id_base->die_id_0); + id[2] = readl(&id_base->die_id_1); + id[1] = readl(&id_base->die_id_2); + id[0] = readl(&id_base->die_id_3); + sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]); + setenv("dieid#", die_id); + uid_s = die_id; + } + + printf("Die ID #%s\n", uid_s); +} + /****************************************** * get_cpu_type(void) - extract cpu info ******************************************/ diff --git a/cpu/i386/Makefile b/cpu/i386/Makefile index f20675af19..e98bd3d7da 100644 --- a/cpu/i386/Makefile +++ b/cpu/i386/Makefile @@ -29,8 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o start16.o resetvec.o -COBJS = serial.o interrupts.o cpu.o timer.o sc520.o -SOBJS = sc520_asm.o +COBJS = serial.o interrupts.o exceptions.o cpu.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/i386/cpu.c b/cpu/i386/cpu.c index b9af5f89d5..d91e33b947 100644 --- a/cpu/i386/cpu.c +++ b/cpu/i386/cpu.c @@ -46,6 +46,10 @@ int cpu_init(void) "orl $0x22, %eax\n" \ "movl %eax, %cr0\n" ); + /* Initialize core interrupt and exception functionality of CPU */ + cpu_init_interrupts (); + cpu_init_exceptions (); + return 0; } diff --git a/cpu/i386/exceptions.c b/cpu/i386/exceptions.c new file mode 100644 index 0000000000..bc3d434601 --- /dev/null +++ b/cpu/i386/exceptions.c @@ -0,0 +1,229 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/interrupt.h> + +asm (".globl exp_return\n" + "exp_return:\n" + " addl $12, %esp\n" + " pop %esp\n" + " popa\n" + " iret\n"); + +char exception_stack[4096]; + +/* + * For detailed description of each exception, refer to: + * Intel® 64 and IA-32 Architectures Software Developer's Manual + * Volume 1: Basic Architecture + * Order Number: 253665-029US, November 2008 + * Table 6-1. Exceptions and Interrupts + */ +DECLARE_EXCEPTION(0, divide_error_entry); +DECLARE_EXCEPTION(1, debug_entry); +DECLARE_EXCEPTION(2, nmi_interrupt_entry); +DECLARE_EXCEPTION(3, breakpoint_entry); +DECLARE_EXCEPTION(4, overflow_entry); +DECLARE_EXCEPTION(5, bound_range_exceeded_entry); +DECLARE_EXCEPTION(6, invalid_opcode_entry); +DECLARE_EXCEPTION(7, device_not_available_entry); +DECLARE_EXCEPTION(8, double_fault_entry); +DECLARE_EXCEPTION(9, coprocessor_segment_overrun_entry); +DECLARE_EXCEPTION(10, invalid_tss_entry); +DECLARE_EXCEPTION(11, segment_not_present_entry); +DECLARE_EXCEPTION(12, stack_segment_fault_entry); +DECLARE_EXCEPTION(13, general_protection_entry); +DECLARE_EXCEPTION(14, page_fault_entry); +DECLARE_EXCEPTION(15, reserved_exception_entry); +DECLARE_EXCEPTION(16, floating_point_error_entry); +DECLARE_EXCEPTION(17, alignment_check_entry); +DECLARE_EXCEPTION(18, machine_check_entry); +DECLARE_EXCEPTION(19, simd_floating_point_exception_entry); +DECLARE_EXCEPTION(20, reserved_exception_entry); +DECLARE_EXCEPTION(21, reserved_exception_entry); +DECLARE_EXCEPTION(22, reserved_exception_entry); +DECLARE_EXCEPTION(23, reserved_exception_entry); +DECLARE_EXCEPTION(24, reserved_exception_entry); +DECLARE_EXCEPTION(25, reserved_exception_entry); +DECLARE_EXCEPTION(26, reserved_exception_entry); +DECLARE_EXCEPTION(27, reserved_exception_entry); +DECLARE_EXCEPTION(28, reserved_exception_entry); +DECLARE_EXCEPTION(29, reserved_exception_entry); +DECLARE_EXCEPTION(30, reserved_exception_entry); +DECLARE_EXCEPTION(31, reserved_exception_entry); + +__isr__ reserved_exception_entry(int cause, int ip, int seg) +{ + printf("Reserved Exception %d at %04x:%08x\n", cause, seg, ip); +} + +__isr__ divide_error_entry(int cause, int ip, int seg) +{ + printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip); + while(1); +} + +__isr__ debug_entry(int cause, int ip, int seg) +{ + printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip); +} + +__isr__ nmi_interrupt_entry(int cause, int ip, int seg) +{ + printf("NMI Interrupt at %04x:%08x\n", seg, ip); +} + +__isr__ breakpoint_entry(int cause, int ip, int seg) +{ + printf("Breakpoint at %04x:%08x\n", seg, ip); +} + +__isr__ overflow_entry(int cause, int ip, int seg) +{ + printf("Overflow at %04x:%08x\n", seg, ip); + while(1); +} + +__isr__ bound_range_exceeded_entry(int cause, int ip, int seg) +{ + printf("BOUND Range Exceeded at %04x:%08x\n", seg, ip); + while(1); +} + +__isr__ invalid_opcode_entry(int cause, int ip, int seg) +{ + printf("Invalid Opcode (UnDefined Opcode) at %04x:%08x\n", seg, ip); + while(1); +} + +__isr__ device_not_available_entry(int cause, int ip, int seg) +{ + printf("Device Not Available (No Math Coprocessor) at %04x:%08x\n", seg, ip); + while(1); +} + +__isr__ double_fault_entry(int cause, int ip, int seg) +{ + printf("Double fault at %04x:%08x\n", seg, ip); + while(1); +} + +__isr__ coprocessor_segment_overrun_entry(int cause, int ip, int seg) +{ + printf("Co-processor segment overrun at %04x:%08x\n", seg, ip); + while(1); +} + +__isr__ invalid_tss_entry(int cause, int ip, int seg) +{ + printf("Invalid TSS at %04x:%08x\n", seg, ip); +} + +__isr__ segment_not_present_entry(int cause, int ip, int seg) +{ + printf("Segment Not Present at %04x:%08x\n", seg, ip); + while(1); +} + +__isr__ stack_segment_fault_entry(int cause, int ip, int seg) +{ + printf("Stack Segment Fault at %04x:%08x\n", seg, ip); + while(1); +} + +__isr__ general_protection_entry(int cause, int ip, int seg) +{ + printf("General Protection at %04x:%08x\n", seg, ip); +} + +__isr__ page_fault_entry(int cause, int ip, int seg) +{ + printf("Page fault at %04x:%08x\n", seg, ip); + while(1); +} + +__isr__ floating_point_error_entry(int cause, int ip, int seg) +{ + printf("Floating-Point Error (Math Fault) at %04x:%08x\n", seg, ip); +} + +__isr__ alignment_check_entry(int cause, int ip, int seg) +{ + printf("Alignment check at %04x:%08x\n", seg, ip); +} + +__isr__ machine_check_entry(int cause, int ip, int seg) +{ + printf("Machine Check at %04x:%08x\n", seg, ip); +} + +__isr__ simd_floating_point_exception_entry(int cause, int ip, int seg) +{ + printf("SIMD Floating-Point Exception at %04x:%08x\n", seg, ip); +} + +int cpu_init_exceptions(void) +{ + /* Just in case... */ + disable_interrupts(); + + /* Setup exceptions */ + set_vector(0x00, exp_0); + set_vector(0x01, exp_1); + set_vector(0x02, exp_2); + set_vector(0x03, exp_3); + set_vector(0x04, exp_4); + set_vector(0x05, exp_5); + set_vector(0x06, exp_6); + set_vector(0x07, exp_7); + set_vector(0x08, exp_8); + set_vector(0x09, exp_9); + set_vector(0x0a, exp_10); + set_vector(0x0b, exp_11); + set_vector(0x0c, exp_12); + set_vector(0x0d, exp_13); + set_vector(0x0e, exp_14); + set_vector(0x0f, exp_15); + set_vector(0x10, exp_16); + set_vector(0x11, exp_17); + set_vector(0x12, exp_18); + set_vector(0x13, exp_19); + set_vector(0x14, exp_20); + set_vector(0x15, exp_21); + set_vector(0x16, exp_22); + set_vector(0x17, exp_23); + set_vector(0x18, exp_24); + set_vector(0x19, exp_25); + set_vector(0x1a, exp_26); + set_vector(0x1b, exp_27); + set_vector(0x1c, exp_28); + set_vector(0x1d, exp_29); + set_vector(0x1e, exp_30); + set_vector(0x1f, exp_31); + + /* It is now safe to enable interrupts */ + enable_interrupts(); + + return 0; +} diff --git a/cpu/i386/interrupts.c b/cpu/i386/interrupts.c index badb30bb8a..063ea42cd2 100644 --- a/cpu/i386/interrupts.c +++ b/cpu/i386/interrupts.c @@ -22,10 +22,6 @@ */ #include <common.h> -#include <malloc.h> -#include <asm/io.h> -#include <asm/i8259.h> -#include <asm/ibmpc.h> #include <asm/interrupt.h> @@ -41,361 +37,34 @@ struct idt_entry { struct idt_entry idt[256]; -#define MAX_IRQ 16 - -typedef struct irq_handler { - struct irq_handler *next; - interrupt_handler_t* isr_func; - void *isr_data; -} irq_handler_t; - -#define IRQ_DISABLED 1 - -typedef struct { - irq_handler_t *handler; - unsigned long status; -} irq_desc_t; - -static irq_desc_t irq_table[MAX_IRQ]; - -asm ("irq_return:\n" +asm (".globl irq_return\n" + "irq_return:\n" " addl $4, %esp\n" " popa\n" " iret\n"); -asm ("exp_return:\n" - " addl $12, %esp\n" - " pop %esp\n" - " popa\n" - " iret\n"); - -char exception_stack[4096]; - -#define DECLARE_INTERRUPT(x) \ - asm(".globl irq_"#x"\n" \ - "irq_"#x":\n" \ - "pusha \n" \ - "pushl $"#x"\n" \ - "pushl $irq_return\n" \ - "jmp do_irq\n"); \ - void __attribute__ ((regparm(0))) irq_##x(void) - -#define DECLARE_EXCEPTION(x, f) \ - asm(".globl exp_"#x"\n" \ - "exp_"#x":\n" \ - "pusha \n" \ - "movl %esp, %ebx\n" \ - "movl $exception_stack, %eax\n" \ - "movl %eax, %esp \n" \ - "pushl %ebx\n" \ - "movl 32(%esp), %ebx\n" \ - "xorl %edx, %edx\n" \ - "movw 36(%esp), %dx\n" \ - "pushl %edx\n" \ - "pushl %ebx\n" \ - "pushl $"#x"\n" \ - "pushl $exp_return\n" \ - "jmp "#f"\n"); \ - void __attribute__ ((regparm(0))) exp_##x(void) - -DECLARE_EXCEPTION(0, divide_exception_entry); /* Divide exception */ -DECLARE_EXCEPTION(1, debug_exception_entry); /* Debug exception */ -DECLARE_EXCEPTION(2, nmi_entry); /* NMI */ -DECLARE_EXCEPTION(3, unknown_exception_entry); /* Breakpoint/Coprocessor Error */ -DECLARE_EXCEPTION(4, unknown_exception_entry); /* Overflow */ -DECLARE_EXCEPTION(5, unknown_exception_entry); /* Bounds */ -DECLARE_EXCEPTION(6, invalid_instruction_entry); /* Invalid instruction */ -DECLARE_EXCEPTION(7, unknown_exception_entry); /* Device not present */ -DECLARE_EXCEPTION(8, double_fault_entry); /* Double fault */ -DECLARE_EXCEPTION(9, unknown_exception_entry); /* Co-processor segment overrun */ -DECLARE_EXCEPTION(10, invalid_tss_exception_entry);/* Invalid TSS */ -DECLARE_EXCEPTION(11, seg_fault_entry); /* Segment not present */ -DECLARE_EXCEPTION(12, stack_fault_entry); /* Stack overflow */ -DECLARE_EXCEPTION(13, gpf_entry); /* GPF */ -DECLARE_EXCEPTION(14, page_fault_entry); /* PF */ -DECLARE_EXCEPTION(15, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(16, fp_exception_entry); /* Floating point */ -DECLARE_EXCEPTION(17, alignment_check_entry); /* alignment check */ -DECLARE_EXCEPTION(18, machine_check_entry); /* machine check */ -DECLARE_EXCEPTION(19, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(20, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(21, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(22, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(23, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(24, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(25, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(26, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(27, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(28, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(29, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(30, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(31, unknown_exception_entry); /* Reserved */ - -DECLARE_INTERRUPT(0); -DECLARE_INTERRUPT(1); -DECLARE_INTERRUPT(3); -DECLARE_INTERRUPT(4); -DECLARE_INTERRUPT(5); -DECLARE_INTERRUPT(6); -DECLARE_INTERRUPT(7); -DECLARE_INTERRUPT(8); -DECLARE_INTERRUPT(9); -DECLARE_INTERRUPT(10); -DECLARE_INTERRUPT(11); -DECLARE_INTERRUPT(12); -DECLARE_INTERRUPT(13); -DECLARE_INTERRUPT(14); -DECLARE_INTERRUPT(15); - void __attribute__ ((regparm(0))) default_isr(void); asm ("default_isr: iret\n"); -void disable_irq(int irq) -{ - if (irq >= MAX_IRQ) { - return; - } - irq_table[irq].status |= IRQ_DISABLED; - -} - -void enable_irq(int irq) -{ - if (irq >= MAX_IRQ) { - return; - } - irq_table[irq].status &= ~IRQ_DISABLED; -} - -/* masks one specific IRQ in the PIC */ -static void unmask_irq(int irq) -{ - int imr_port; - - if (irq >= MAX_IRQ) { - return; - } - if (irq > 7) { - imr_port = SLAVE_PIC + IMR; - } else { - imr_port = MASTER_PIC + IMR; - } - - outb(inb(imr_port)&~(1<<(irq&7)), imr_port); -} - - -/* unmasks one specific IRQ in the PIC */ -static void mask_irq(int irq) -{ - int imr_port; - - if (irq >= MAX_IRQ) { - return; - } - if (irq > 7) { - imr_port = SLAVE_PIC + IMR; - } else { - imr_port = MASTER_PIC + IMR; - } - - outb(inb(imr_port)|(1<<(irq&7)), imr_port); -} - - -/* issue a Specific End Of Interrupt instruciton */ -static void specific_eoi(int irq) -{ - /* If it is on the slave PIC this have to be performed on - * both the master and the slave PICs */ - if (irq > 7) { - outb(OCW2_SEOI|(irq&7), SLAVE_PIC + OCW2); - irq = SEOI_IR2; /* also do IR2 on master */ - } - outb(OCW2_SEOI|irq, MASTER_PIC + OCW2); -} - -void __attribute__ ((regparm(0))) do_irq(int irq) -{ - - mask_irq(irq); - - if (irq_table[irq].status & IRQ_DISABLED) { - unmask_irq(irq); - specific_eoi(irq); - return; - } - - - if (NULL != irq_table[irq].handler) { - irq_handler_t *handler; - for (handler = irq_table[irq].handler; - NULL!= handler; handler = handler->next) { - handler->isr_func(handler->isr_data); - } - } else { - if ((irq & 7) != 7) { - printf("Spurious irq %d\n", irq); - } - } - unmask_irq(irq); - specific_eoi(irq); -} - - -void __attribute__ ((regparm(0))) unknown_exception_entry(int cause, int ip, int seg) -{ - printf("Unknown Exception %d at %04x:%08x\n", cause, seg, ip); -} - -void __attribute__ ((regparm(0))) divide_exception_entry(int cause, int ip, int seg) -{ - printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip); - while(1); -} - -void __attribute__ ((regparm(0))) debug_exception_entry(int cause, int ip, int seg) -{ - printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip); -} - -void __attribute__ ((regparm(0))) nmi_entry(int cause, int ip, int seg) -{ - printf("NMI Interrupt at %04x:%08x\n", seg, ip); -} - -void __attribute__ ((regparm(0))) invalid_instruction_entry(int cause, int ip, int seg) -{ - printf("Invalid Instruction at %04x:%08x\n", seg, ip); - while(1); -} - -void __attribute__ ((regparm(0))) double_fault_entry(int cause, int ip, int seg) -{ - printf("Double fault at %04x:%08x\n", seg, ip); - while(1); -} - -void __attribute__ ((regparm(0))) invalid_tss_exception_entry(int cause, int ip, int seg) -{ - printf("Invalid TSS at %04x:%08x\n", seg, ip); -} - -void __attribute__ ((regparm(0))) seg_fault_entry(int cause, int ip, int seg) -{ - printf("Segmentation fault at %04x:%08x\n", seg, ip); - while(1); -} - -void __attribute__ ((regparm(0))) stack_fault_entry(int cause, int ip, int seg) -{ - printf("Stack fault at %04x:%08x\n", seg, ip); - while(1); -} - -void __attribute__ ((regparm(0))) gpf_entry(int cause, int ip, int seg) -{ - printf("General protection fault at %04x:%08x\n", seg, ip); -} - -void __attribute__ ((regparm(0))) page_fault_entry(int cause, int ip, int seg) -{ - printf("Page fault at %04x:%08x\n", seg, ip); - while(1); -} - -void __attribute__ ((regparm(0))) fp_exception_entry(int cause, int ip, int seg) -{ - printf("Floating point exception at %04x:%08x\n", seg, ip); -} - -void __attribute__ ((regparm(0))) alignment_check_entry(int cause, int ip, int seg) -{ - printf("Alignment check at %04x:%08x\n", seg, ip); -} - -void __attribute__ ((regparm(0))) machine_check_entry(int cause, int ip, int seg) -{ - printf("Machine check exception at %04x:%08x\n", seg, ip); -} - - -void irq_install_handler(int ino, interrupt_handler_t *func, void *pdata) -{ - int status; - - if (ino>MAX_IRQ) { - return; - } - - if (NULL != irq_table[ino].handler) { - return; - } - - status = disable_interrupts(); - irq_table[ino].handler = malloc(sizeof(irq_handler_t)); - if (NULL == irq_table[ino].handler) { - return; - } - - memset(irq_table[ino].handler, 0, sizeof(irq_handler_t)); - - irq_table[ino].handler->isr_func = func; - irq_table[ino].handler->isr_data = pdata; - if (status) { - enable_interrupts(); - } - - unmask_irq(ino); - - return; -} - -void irq_free_handler(int ino) -{ - int status; - if (ino>MAX_IRQ) { - return; - } - - status = disable_interrupts(); - mask_irq(ino); - if (NULL == irq_table[ino].handler) { - return; - } - free(irq_table[ino].handler); - irq_table[ino].handler=NULL; - if (status) { - enable_interrupts(); - } - return; -} - - asm ("idt_ptr:\n" ".word 0x800\n" /* size of the table 8*256 bytes */ ".long idt\n" /* offset */ ".word 0x18\n");/* data segment */ -void set_vector(int intnum, void *routine) +void set_vector(u8 intnum, void *routine) { - idt[intnum].base_high = (u16)((u32)(routine)>>16); - idt[intnum].base_low = (u16)((u32)(routine)&0xffff); + idt[intnum].base_high = (u16)((u32)(routine + gd->reloc_off) >> 16); + idt[intnum].base_low = (u16)((u32)(routine + gd->reloc_off) & 0xffff); } -int interrupt_init(void) +int cpu_init_interrupts(void) { int i; /* Just in case... */ disable_interrupts(); - /* Initialize the IDT and stuff */ - - - memset(irq_table, 0, sizeof(irq_table)); - /* Setup the IDT */ for (i=0;i<256;i++) { idt[i].access = 0x8e; @@ -406,89 +75,6 @@ int interrupt_init(void) asm ("cs lidt idt_ptr\n"); - /* Setup exceptions */ - set_vector(0x00, exp_0); - set_vector(0x01, exp_1); - set_vector(0x02, exp_2); - set_vector(0x03, exp_3); - set_vector(0x04, exp_4); - set_vector(0x05, exp_5); - set_vector(0x06, exp_6); - set_vector(0x07, exp_7); - set_vector(0x08, exp_8); - set_vector(0x09, exp_9); - set_vector(0x0a, exp_10); - set_vector(0x0b, exp_11); - set_vector(0x0c, exp_12); - set_vector(0x0d, exp_13); - set_vector(0x0e, exp_14); - set_vector(0x0f, exp_15); - set_vector(0x10, exp_16); - set_vector(0x11, exp_17); - set_vector(0x12, exp_18); - set_vector(0x13, exp_19); - set_vector(0x14, exp_20); - set_vector(0x15, exp_21); - set_vector(0x16, exp_22); - set_vector(0x17, exp_23); - set_vector(0x18, exp_24); - set_vector(0x19, exp_25); - set_vector(0x1a, exp_26); - set_vector(0x1b, exp_27); - set_vector(0x1c, exp_28); - set_vector(0x1d, exp_29); - set_vector(0x1e, exp_30); - set_vector(0x1f, exp_31); - - - /* Setup interrupts */ - set_vector(0x20, irq_0); - set_vector(0x21, irq_1); - set_vector(0x23, irq_3); - set_vector(0x24, irq_4); - set_vector(0x25, irq_5); - set_vector(0x26, irq_6); - set_vector(0x27, irq_7); - set_vector(0x28, irq_8); - set_vector(0x29, irq_9); - set_vector(0x2a, irq_10); - set_vector(0x2b, irq_11); - set_vector(0x2c, irq_12); - set_vector(0x2d, irq_13); - set_vector(0x2e, irq_14); - set_vector(0x2f, irq_15); - /* vectors 0x30-0x3f are reserved for irq 16-31 */ - - - /* Mask all interrupts */ - outb(0xff, MASTER_PIC + IMR); - outb(0xff, SLAVE_PIC + IMR); - - /* Master PIC */ - outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1); - outb(0x20, MASTER_PIC + ICW2); /* Place master PIC interrupts at INT20 */ - outb(IR2, MASTER_PIC + ICW3); /* ICW3, One slevc PIC is present */ - outb(ICW4_PM, MASTER_PIC + ICW4); - - for (i=0;i<8;i++) { - outb(OCW2_SEOI|i, MASTER_PIC + OCW2); - } - - /* Slave PIC */ - outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1); - outb(0x28, SLAVE_PIC + ICW2); /* Place slave PIC interrupts at INT28 */ - outb(0x02, SLAVE_PIC + ICW3); /* Slave ID */ - outb(ICW4_PM, SLAVE_PIC + ICW4); - - for (i=0;i<8;i++) { - outb(OCW2_SEOI|i, SLAVE_PIC + OCW2); - } - - - /* enable cascade interrerupt */ - outb(0xfb, MASTER_PIC + IMR); - outb(0xff, SLAVE_PIC + IMR); - /* It is now safe to enable interrupts */ enable_interrupts(); diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c deleted file mode 100644 index b958f8dc04..0000000000 --- a/cpu/i386/sc520.c +++ /dev/null @@ -1,516 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* stuff specific for the sc520, - * but idependent of implementation */ - -#include <config.h> -#include <common.h> -#include <config.h> -#include <pci.h> -#ifdef CONFIG_SC520_SSI -#include <asm/ic/ssi.h> -#endif -#include <asm/io.h> -#include <asm/pci.h> -#include <asm/ic/sc520.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * utility functions for boards based on the AMD sc520 - * - * void write_mmcr_byte(u16 mmcr, u8 data) - * void write_mmcr_word(u16 mmcr, u16 data) - * void write_mmcr_long(u16 mmcr, u32 data) - * - * u8 read_mmcr_byte(u16 mmcr) - * u16 read_mmcr_word(u16 mmcr) - * u32 read_mmcr_long(u16 mmcr) - * - * void init_sc520(void) - * unsigned long init_sc520_dram(void) - * void pci_sc520_init(struct pci_controller *hose) - * - * void reset_timer(void) - * ulong get_timer(ulong base) - * void set_timer(ulong t) - * void udelay(unsigned long usec) - * - */ - -static u32 mmcr_base= 0xfffef000; - -void write_mmcr_byte(u16 mmcr, u8 data) -{ - writeb(data, mmcr+mmcr_base); -} - -void write_mmcr_word(u16 mmcr, u16 data) -{ - writew(data, mmcr+mmcr_base); -} - -void write_mmcr_long(u16 mmcr, u32 data) -{ - writel(data, mmcr+mmcr_base); -} - -u8 read_mmcr_byte(u16 mmcr) -{ - return readb(mmcr+mmcr_base); -} - -u16 read_mmcr_word(u16 mmcr) -{ - return readw(mmcr+mmcr_base); -} - -u32 read_mmcr_long(u16 mmcr) -{ - return readl(mmcr+mmcr_base); -} - - -void init_sc520(void) -{ - /* Set the UARTxCTL register at it's slower, - * baud clock giving us a 1.8432 MHz reference - */ - write_mmcr_byte(SC520_UART1CTL, 7); - write_mmcr_byte(SC520_UART2CTL, 7); - - /* first set the timer pin mapping */ - write_mmcr_byte(SC520_CLKSEL, 0x72); /* no clock frequency selected, use 1.1892MHz */ - - /* enable PCI bus arbitrer */ - write_mmcr_byte(SC520_SYSARBCTL,0x02); /* enable concurrent mode */ - - write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */ - write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */ - - - if (CONFIG_SYS_SC520_HIGH_SPEED) { - write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */ - gd->cpu_clk = 133000000; - printf("## CPU Speed set to 133MHz\n"); - } else { - write_mmcr_byte(SC520_CPUCTL, 1); /* set CPU to 100 MHz and write back cache */ - printf("## CPU Speed set to 100MHz\n"); - gd->cpu_clk = 100000000; - } - - - /* wait at least one millisecond */ - asm("movl $0x2000,%%ecx\n" - "wait_loop: pushl %%ecx\n" - "popl %%ecx\n" - "loop wait_loop\n": : : "ecx"); - - /* turn on the SDRAM write buffer */ - write_mmcr_byte(SC520_DBCTL, 0x11); - - /* turn on the cache and disable write through */ - asm("movl %%cr0, %%eax\n" - "andl $0x9fffffff, %%eax\n" - "movl %%eax, %%cr0\n" : : : "eax"); -} - -unsigned long init_sc520_dram(void) -{ - bd_t *bd = gd->bd; - - u32 dram_present=0; - u32 dram_ctrl; -#ifdef CONFIG_SYS_SDRAM_DRCTMCTL - /* these memory control registers are set up in the assember part, - * in sc520_asm.S, during 'mem_init'. If we muck with them here, - * after we are running a stack in RAM, we have troubles. Besides, - * these refresh and delay values are better ? simply specified - * outright in the include/configs/{cfg} file since the HW designer - * simply dictates it. - */ -#else - int val; - - int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY; - int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE; - int ras_cas_delay = CONFIG_SYS_SDRAM_RAS_CAS_DELAY; - - /* set SDRAM speed here */ - - refresh_rate/=78; - if (refresh_rate<=1) { - val = 0; /* 7.8us */ - } else if (refresh_rate==2) { - val = 1; /* 15.6us */ - } else if (refresh_rate==3 || refresh_rate==4) { - val = 2; /* 31.2us */ - } else { - val = 3; /* 62.4us */ - } - - write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4)); - - val = read_mmcr_byte(SC520_DRCTMCTL); - val &= 0xf0; - - if (cas_precharge_delay==3) { - val |= 0x04; /* 3T */ - } else if (cas_precharge_delay==4) { - val |= 0x08; /* 4T */ - } else if (cas_precharge_delay>4) { - val |= 0x0c; - } - - if (ras_cas_delay > 3) { - val |= 2; - } else { - val |= 1; - } - write_mmcr_byte(SC520_DRCTMCTL, val); -#endif - - /* We read-back the configuration of the dram - * controller that the assembly code wrote */ - dram_ctrl = read_mmcr_long(SC520_DRCBENDADR); - - bd->bi_dram[0].start = 0; - if (dram_ctrl & 0x80) { - /* bank 0 enabled */ - dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22; - bd->bi_dram[0].size = bd->bi_dram[1].start; - - } else { - bd->bi_dram[0].size = 0; - bd->bi_dram[1].start = bd->bi_dram[0].start; - } - - if (dram_ctrl & 0x8000) { - /* bank 1 enabled */ - dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14; - bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start; - } else { - bd->bi_dram[1].size = 0; - bd->bi_dram[2].start = bd->bi_dram[1].start; - } - - if (dram_ctrl & 0x800000) { - /* bank 2 enabled */ - dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6; - bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start; - } else { - bd->bi_dram[2].size = 0; - bd->bi_dram[3].start = bd->bi_dram[2].start; - } - - if (dram_ctrl & 0x80000000) { - /* bank 3 enabled */ - dram_present = (dram_ctrl & 0x7f000000) >> 2; - bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start; - } else { - bd->bi_dram[3].size = 0; - } - - -#if 0 - printf("Configured %d bytes of dram\n", dram_present); -#endif - gd->ram_size = dram_present; - - return dram_present; -} - - -#ifdef CONFIG_PCI - - -static struct { - u8 priority; - u16 level_reg; - u8 level_bit; -} sc520_irq[] = { - { SC520_IRQ0, SC520_MPICMODE, 0x01 }, - { SC520_IRQ1, SC520_MPICMODE, 0x02 }, - { SC520_IRQ2, SC520_SL1PICMODE, 0x02 }, - { SC520_IRQ3, SC520_MPICMODE, 0x08 }, - { SC520_IRQ4, SC520_MPICMODE, 0x10 }, - { SC520_IRQ5, SC520_MPICMODE, 0x20 }, - { SC520_IRQ6, SC520_MPICMODE, 0x40 }, - { SC520_IRQ7, SC520_MPICMODE, 0x80 }, - - { SC520_IRQ8, SC520_SL1PICMODE, 0x01 }, - { SC520_IRQ9, SC520_SL1PICMODE, 0x02 }, - { SC520_IRQ10, SC520_SL1PICMODE, 0x04 }, - { SC520_IRQ11, SC520_SL1PICMODE, 0x08 }, - { SC520_IRQ12, SC520_SL1PICMODE, 0x10 }, - { SC520_IRQ13, SC520_SL1PICMODE, 0x20 }, - { SC520_IRQ14, SC520_SL1PICMODE, 0x40 }, - { SC520_IRQ15, SC520_SL1PICMODE, 0x80 } -}; - - -/* The interrupt used for PCI INTA-INTD */ -int sc520_pci_ints[15] = { - -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1 -}; - -/* utility function to configure a pci interrupt */ -int pci_sc520_set_irq(int pci_pin, int irq) -{ - int i; - -# if 1 - printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); -#endif - if (irq < 0 || irq > 15) { - return -1; /* illegal irq */ - } - - if (pci_pin < 0 || pci_pin > 15) { - return -1; /* illegal pci int pin */ - } - - /* first disable any non-pci interrupt source that use - * this level */ - for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) { - if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) { - continue; - } - if (read_mmcr_byte(i) == sc520_irq[irq].priority) { - write_mmcr_byte(i, SC520_IRQ_DISABLED); - } - } - - /* Set the trigger to level */ - write_mmcr_byte(sc520_irq[irq].level_reg, - read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit); - - - if (pci_pin < 4) { - /* PCI INTA-INTD */ - /* route the interrupt */ - write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority); - - - } else { - /* GPIRQ0-GPIRQ10 used for additional PCI INTS */ - write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority); - - /* also set the polarity in this case */ - write_mmcr_word(SC520_INTPINPOL, - read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4))); - - } - - /* register the pin */ - sc520_pci_ints[pci_pin] = irq; - - - return 0; /* OK */ -} - -void pci_sc520_init(struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region(hose->regions + 0, - SC520_PCI_MEMORY_BUS, - SC520_PCI_MEMORY_PHYS, - SC520_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - SC520_PCI_MEM_BUS, - SC520_PCI_MEM_PHYS, - SC520_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* ISA/PCI memory space */ - pci_set_region(hose->regions + 2, - SC520_ISA_MEM_BUS, - SC520_ISA_MEM_PHYS, - SC520_ISA_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(hose->regions + 3, - SC520_PCI_IO_BUS, - SC520_PCI_IO_PHYS, - SC520_PCI_IO_SIZE, - PCI_REGION_IO); - - /* ISA/PCI I/O space */ - pci_set_region(hose->regions + 4, - SC520_ISA_IO_BUS, - SC520_ISA_IO_PHYS, - SC520_ISA_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 5; - - pci_setup_type1(hose, - SC520_REG_ADDR, - SC520_REG_DATA); - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); - - /* enable target memory acceses on host brige */ - pci_write_config_word(0, PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - -} - - -#endif - -#ifdef CONFIG_SYS_TIMER_SC520 - - -void reset_timer(void) -{ - write_mmcr_word(SC520_GPTMR0CNT, 0); - write_mmcr_word(SC520_GPTMR0CTL, 0x6001); - -} - -ulong get_timer(ulong base) -{ - /* fixme: 30 or 33 */ - return read_mmcr_word(SC520_GPTMR0CNT) / 33; -} - -void set_timer(ulong t) -{ - /* FixMe: use two cascade coupled timers */ - write_mmcr_word(SC520_GPTMR0CTL, 0x4001); - write_mmcr_word(SC520_GPTMR0CNT, t*33); - write_mmcr_word(SC520_GPTMR0CTL, 0x6001); -} - - -void udelay(unsigned long usec) -{ - int m=0; - long u; - - read_mmcr_word(SC520_SWTMRMILLI); - read_mmcr_word(SC520_SWTMRMICRO); - -#if 0 - /* do not enable this line, udelay is used in the serial driver -> recursion */ - printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec, m, u, tm, tu); -#endif - while (1) { - - m += read_mmcr_word(SC520_SWTMRMILLI); - u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000); - - if (usec <= u) { - break; - } - } -} - -#endif - -int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase) -{ - u8 temp=0; - - if (freq >= 8192) { - temp |= CTL_CLK_SEL_4; - } else if (freq >= 4096) { - temp |= CTL_CLK_SEL_8; - } else if (freq >= 2048) { - temp |= CTL_CLK_SEL_16; - } else if (freq >= 1024) { - temp |= CTL_CLK_SEL_32; - } else if (freq >= 512) { - temp |= CTL_CLK_SEL_64; - } else if (freq >= 256) { - temp |= CTL_CLK_SEL_128; - } else if (freq >= 128) { - temp |= CTL_CLK_SEL_256; - } else { - temp |= CTL_CLK_SEL_512; - } - - if (!lsb_first) { - temp |= MSBF_ENB; - } - - if (inv_clock) { - temp |= CLK_INV_ENB; - } - - if (inv_phase) { - temp |= PHS_INV_ENB; - } - - write_mmcr_byte(SC520_SSICTL, temp); - - return 0; -} - -u8 ssi_txrx_byte(u8 data) -{ - write_mmcr_byte(SC520_SSIXMIT, data); - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV); - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - return read_mmcr_byte(SC520_SSIRCV); -} - - -void ssi_tx_byte(u8 data) -{ - write_mmcr_byte(SC520_SSIXMIT, data); - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT); -} - -u8 ssi_rx_byte(void) -{ - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV); - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - return read_mmcr_byte(SC520_SSIRCV); -} - -#ifdef CONFIG_SYS_RESET_SC520 -void reset_cpu(ulong addr) -{ - printf("Resetting using SC520 MMCR\n"); - /* Write a '1' to the SYS_RST of the RESCFG MMCR */ - write_mmcr_word(SC520_RESCFG, 0x0001); - - /* NOTREACHED */ -} -#endif diff --git a/cpu/i386/sc520/Makefile b/cpu/i386/sc520/Makefile new file mode 100644 index 0000000000..87835b2c20 --- /dev/null +++ b/cpu/i386/sc520/Makefile @@ -0,0 +1,56 @@ +# +# (C) Copyright 2008 +# Graeme Russ, graeme.russ@gmail.com. +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(SOC).a + +COBJS-$(CONFIG_SYS_SC520) += sc520.o +COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o +COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o +COBJS-$(CONFIG_PCI) += sc520_pci.o + +SOBJS-$(CONFIG_SYS_SC520) += sc520_asm.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +#########################################################################
\ No newline at end of file diff --git a/cpu/i386/sc520/sc520.c b/cpu/i386/sc520/sc520.c new file mode 100644 index 0000000000..ae3b50007f --- /dev/null +++ b/cpu/i386/sc520/sc520.c @@ -0,0 +1,239 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* stuff specific for the sc520, + * but idependent of implementation */ + +#include <common.h> +#include <asm/io.h> +#include <asm/ic/sc520.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * utility functions for boards based on the AMD sc520 + * + * void write_mmcr_byte(u16 mmcr, u8 data) + * void write_mmcr_word(u16 mmcr, u16 data) + * void write_mmcr_long(u16 mmcr, u32 data) + * + * u8 read_mmcr_byte(u16 mmcr) + * u16 read_mmcr_word(u16 mmcr) + * u32 read_mmcr_long(u16 mmcr) + * + * void init_sc520(void) + * unsigned long init_sc520_dram(void) + */ + +static u32 mmcr_base= 0xfffef000; + +void write_mmcr_byte(u16 mmcr, u8 data) +{ + writeb(data, mmcr+mmcr_base); +} + +void write_mmcr_word(u16 mmcr, u16 data) +{ + writew(data, mmcr+mmcr_base); +} + +void write_mmcr_long(u16 mmcr, u32 data) +{ + writel(data, mmcr+mmcr_base); +} + +u8 read_mmcr_byte(u16 mmcr) +{ + return readb(mmcr+mmcr_base); +} + +u16 read_mmcr_word(u16 mmcr) +{ + return readw(mmcr+mmcr_base); +} + +u32 read_mmcr_long(u16 mmcr) +{ + return readl(mmcr+mmcr_base); +} + + +void init_sc520(void) +{ + /* Set the UARTxCTL register at it's slower, + * baud clock giving us a 1.8432 MHz reference + */ + write_mmcr_byte(SC520_UART1CTL, 7); + write_mmcr_byte(SC520_UART2CTL, 7); + + /* first set the timer pin mapping */ + write_mmcr_byte(SC520_CLKSEL, 0x72); /* no clock frequency selected, use 1.1892MHz */ + + /* enable PCI bus arbitrer */ + write_mmcr_byte(SC520_SYSARBCTL,0x02); /* enable concurrent mode */ + + write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */ + write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */ + + + if (CONFIG_SYS_SC520_HIGH_SPEED) { + write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */ + gd->cpu_clk = 133000000; + printf("## CPU Speed set to 133MHz\n"); + } else { + write_mmcr_byte(SC520_CPUCTL, 1); /* set CPU to 100 MHz and write back cache */ + printf("## CPU Speed set to 100MHz\n"); + gd->cpu_clk = 100000000; + } + + + /* wait at least one millisecond */ + asm("movl $0x2000,%%ecx\n" + "wait_loop: pushl %%ecx\n" + "popl %%ecx\n" + "loop wait_loop\n": : : "ecx"); + + /* turn on the SDRAM write buffer */ + write_mmcr_byte(SC520_DBCTL, 0x11); + + /* turn on the cache and disable write through */ + asm("movl %%cr0, %%eax\n" + "andl $0x9fffffff, %%eax\n" + "movl %%eax, %%cr0\n" : : : "eax"); +} + +unsigned long init_sc520_dram(void) +{ + bd_t *bd = gd->bd; + + u32 dram_present=0; + u32 dram_ctrl; +#ifdef CONFIG_SYS_SDRAM_DRCTMCTL + /* these memory control registers are set up in the assember part, + * in sc520_asm.S, during 'mem_init'. If we muck with them here, + * after we are running a stack in RAM, we have troubles. Besides, + * these refresh and delay values are better ? simply specified + * outright in the include/configs/{cfg} file since the HW designer + * simply dictates it. + */ +#else + int val; + + int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY; + int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE; + int ras_cas_delay = CONFIG_SYS_SDRAM_RAS_CAS_DELAY; + + /* set SDRAM speed here */ + + refresh_rate/=78; + if (refresh_rate<=1) { + val = 0; /* 7.8us */ + } else if (refresh_rate==2) { + val = 1; /* 15.6us */ + } else if (refresh_rate==3 || refresh_rate==4) { + val = 2; /* 31.2us */ + } else { + val = 3; /* 62.4us */ + } + + write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4)); + + val = read_mmcr_byte(SC520_DRCTMCTL); + val &= 0xf0; + + if (cas_precharge_delay==3) { + val |= 0x04; /* 3T */ + } else if (cas_precharge_delay==4) { + val |= 0x08; /* 4T */ + } else if (cas_precharge_delay>4) { + val |= 0x0c; + } + + if (ras_cas_delay > 3) { + val |= 2; + } else { + val |= 1; + } + write_mmcr_byte(SC520_DRCTMCTL, val); +#endif + + /* We read-back the configuration of the dram + * controller that the assembly code wrote */ + dram_ctrl = read_mmcr_long(SC520_DRCBENDADR); + + bd->bi_dram[0].start = 0; + if (dram_ctrl & 0x80) { + /* bank 0 enabled */ + dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22; + bd->bi_dram[0].size = bd->bi_dram[1].start; + + } else { + bd->bi_dram[0].size = 0; + bd->bi_dram[1].start = bd->bi_dram[0].start; + } + + if (dram_ctrl & 0x8000) { + /* bank 1 enabled */ + dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14; + bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start; + } else { + bd->bi_dram[1].size = 0; + bd->bi_dram[2].start = bd->bi_dram[1].start; + } + + if (dram_ctrl & 0x800000) { + /* bank 2 enabled */ + dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6; + bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start; + } else { + bd->bi_dram[2].size = 0; + bd->bi_dram[3].start = bd->bi_dram[2].start; + } + + if (dram_ctrl & 0x80000000) { + /* bank 3 enabled */ + dram_present = (dram_ctrl & 0x7f000000) >> 2; + bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start; + } else { + bd->bi_dram[3].size = 0; + } + + +#if 0 + printf("Configured %d bytes of dram\n", dram_present); +#endif + gd->ram_size = dram_present; + + return dram_present; +} + +#ifdef CONFIG_SYS_SC520_RESET +void reset_cpu(ulong addr) +{ + printf("Resetting using SC520 MMCR\n"); + /* Write a '1' to the SYS_RST of the RESCFG MMCR */ + write_mmcr_word(SC520_RESCFG, 0x0001); + + /* NOTREACHED */ +} +#endif diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520/sc520_asm.S index 59ed2b8d65..2042d9bfcf 100644 --- a/cpu/i386/sc520_asm.S +++ b/cpu/i386/sc520/sc520_asm.S @@ -105,7 +105,6 @@ */ #include <config.h> -#ifdef CONFIG_SC520 .section .text .equ DRCCTL, 0x0fffef010 /* DRAM control register */ @@ -580,5 +579,3 @@ set_ecc: out: movl %ebx, %eax jmp *%ebp - -#endif /* CONFIG_SC520 */ diff --git a/cpu/i386/sc520/sc520_pci.c b/cpu/i386/sc520/sc520_pci.c new file mode 100644 index 0000000000..38b837e81c --- /dev/null +++ b/cpu/i386/sc520/sc520_pci.c @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* stuff specific for the sc520, but independent of implementation */ + +#include <common.h> +#include <pci.h> +#include <asm/pci.h> +#include <asm/ic/sc520.h> + +static struct { + u8 priority; + u16 level_reg; + u8 level_bit; +} sc520_irq[] = { + { SC520_IRQ0, SC520_MPICMODE, 0x01 }, + { SC520_IRQ1, SC520_MPICMODE, 0x02 }, + { SC520_IRQ2, SC520_SL1PICMODE, 0x02 }, + { SC520_IRQ3, SC520_MPICMODE, 0x08 }, + { SC520_IRQ4, SC520_MPICMODE, 0x10 }, + { SC520_IRQ5, SC520_MPICMODE, 0x20 }, + { SC520_IRQ6, SC520_MPICMODE, 0x40 }, + { SC520_IRQ7, SC520_MPICMODE, 0x80 }, + + { SC520_IRQ8, SC520_SL1PICMODE, 0x01 }, + { SC520_IRQ9, SC520_SL1PICMODE, 0x02 }, + { SC520_IRQ10, SC520_SL1PICMODE, 0x04 }, + { SC520_IRQ11, SC520_SL1PICMODE, 0x08 }, + { SC520_IRQ12, SC520_SL1PICMODE, 0x10 }, + { SC520_IRQ13, SC520_SL1PICMODE, 0x20 }, + { SC520_IRQ14, SC520_SL1PICMODE, 0x40 }, + { SC520_IRQ15, SC520_SL1PICMODE, 0x80 } +}; + + +/* The interrupt used for PCI INTA-INTD */ +int sc520_pci_ints[15] = { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1 +}; + +/* utility function to configure a pci interrupt */ +int pci_sc520_set_irq(int pci_pin, int irq) +{ + int i; + +# if 1 + printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); +#endif + if (irq < 0 || irq > 15) { + return -1; /* illegal irq */ + } + + if (pci_pin < 0 || pci_pin > 15) { + return -1; /* illegal pci int pin */ + } + + /* first disable any non-pci interrupt source that use + * this level */ + for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) { + if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) { + continue; + } + if (read_mmcr_byte(i) == sc520_irq[irq].priority) { + write_mmcr_byte(i, SC520_IRQ_DISABLED); + } + } + + /* Set the trigger to level */ + write_mmcr_byte(sc520_irq[irq].level_reg, + read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit); + + + if (pci_pin < 4) { + /* PCI INTA-INTD */ + /* route the interrupt */ + write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority); + + + } else { + /* GPIRQ0-GPIRQ10 used for additional PCI INTS */ + write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority); + + /* also set the polarity in this case */ + write_mmcr_word(SC520_INTPINPOL, + read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4))); + + } + + /* register the pin */ + sc520_pci_ints[pci_pin] = irq; + + + return 0; /* OK */ +} + +void pci_sc520_init(struct pci_controller *hose) +{ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* System memory space */ + pci_set_region(hose->regions + 0, + SC520_PCI_MEMORY_BUS, + SC520_PCI_MEMORY_PHYS, + SC520_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + SC520_PCI_MEM_BUS, + SC520_PCI_MEM_PHYS, + SC520_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* ISA/PCI memory space */ + pci_set_region(hose->regions + 2, + SC520_ISA_MEM_BUS, + SC520_ISA_MEM_PHYS, + SC520_ISA_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(hose->regions + 3, + SC520_PCI_IO_BUS, + SC520_PCI_IO_PHYS, + SC520_PCI_IO_SIZE, + PCI_REGION_IO); + + /* ISA/PCI I/O space */ + pci_set_region(hose->regions + 4, + SC520_ISA_IO_BUS, + SC520_ISA_IO_PHYS, + SC520_ISA_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 5; + + pci_setup_type1(hose, + SC520_REG_ADDR, + SC520_REG_DATA); + + pci_register_hose(hose); + + hose->last_busno = pci_hose_scan(hose); + + /* enable target memory acceses on host brige */ + pci_write_config_word(0, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + +} diff --git a/cpu/i386/sc520/sc520_ssi.c b/cpu/i386/sc520/sc520_ssi.c new file mode 100644 index 0000000000..dd667ca8cb --- /dev/null +++ b/cpu/i386/sc520/sc520_ssi.c @@ -0,0 +1,92 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* stuff specific for the sc520, but independent of implementation */ + +#include <common.h> +#include <asm/ic/ssi.h> +#include <asm/ic/sc520.h> + +int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase) +{ + u8 temp=0; + + if (freq >= 8192) { + temp |= CTL_CLK_SEL_4; + } else if (freq >= 4096) { + temp |= CTL_CLK_SEL_8; + } else if (freq >= 2048) { + temp |= CTL_CLK_SEL_16; + } else if (freq >= 1024) { + temp |= CTL_CLK_SEL_32; + } else if (freq >= 512) { + temp |= CTL_CLK_SEL_64; + } else if (freq >= 256) { + temp |= CTL_CLK_SEL_128; + } else if (freq >= 128) { + temp |= CTL_CLK_SEL_256; + } else { + temp |= CTL_CLK_SEL_512; + } + + if (!lsb_first) { + temp |= MSBF_ENB; + } + + if (inv_clock) { + temp |= CLK_INV_ENB; + } + + if (inv_phase) { + temp |= PHS_INV_ENB; + } + + write_mmcr_byte(SC520_SSICTL, temp); + + return 0; +} + +u8 ssi_txrx_byte(u8 data) +{ + write_mmcr_byte(SC520_SSIXMIT, data); + while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); + write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV); + while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); + return read_mmcr_byte(SC520_SSIRCV); +} + + +void ssi_tx_byte(u8 data) +{ + write_mmcr_byte(SC520_SSIXMIT, data); + while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); + write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT); +} + +u8 ssi_rx_byte(void) +{ + while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); + write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV); + while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); + return read_mmcr_byte(SC520_SSIRCV); +} diff --git a/cpu/i386/sc520/sc520_timer.c b/cpu/i386/sc520/sc520_timer.c new file mode 100644 index 0000000000..2cb8656ebd --- /dev/null +++ b/cpu/i386/sc520/sc520_timer.c @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* stuff specific for the sc520, but independent of implementation */ + +#include <common.h> +#include <asm/interrupt.h> +#include <asm/ic/sc520.h> + +void sc520_timer_isr(void) +{ + /* Ack the GP Timer Interrupt */ + write_mmcr_byte (SC520_GPTMRSTA, 0x02); +} + +int timer_init(void) +{ + /* Map GP Timer 1 to Master PIC IR0 */ + write_mmcr_byte (SC520_GPTMR1MAP, 0x01); + + /* Disable GP Timers 1 & 2 - Allow configuration writes */ + write_mmcr_word (SC520_GPTMR1CTL, 0x4000); + write_mmcr_word (SC520_GPTMR2CTL, 0x4000); + + /* Reset GP Timers 1 & 2 */ + write_mmcr_word (SC520_GPTMR1CNT, 0x0000); + write_mmcr_word (SC520_GPTMR2CNT, 0x0000); + + /* Setup GP Timer 2 as a 100kHz (10us) prescaler */ + write_mmcr_word (SC520_GPTMR2MAXCMPA, 83); + write_mmcr_word (SC520_GPTMR2CTL, 0xc001); + + /* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */ + write_mmcr_word (SC520_GPTMR1MAXCMPA, 100); + write_mmcr_word (SC520_GPTMR1CTL, 0xe009); + + /* Clear the GP Timers status register */ + write_mmcr_byte (SC520_GPTMRSTA, 0x07); + + /* Register the SC520 specific timer interrupt handler */ + register_timer_isr (sc520_timer_isr); + + /* Install interrupt handler for GP Timer 1 */ + irq_install_handler (0, timer_isr, NULL); + unmask_irq (0); + + return 0; +} + +void udelay(unsigned long usec) +{ + int m = 0; + long u; + + read_mmcr_word (SC520_SWTMRMILLI); + read_mmcr_word (SC520_SWTMRMICRO); + + do { + m += read_mmcr_word (SC520_SWTMRMILLI); + u = read_mmcr_word (SC520_SWTMRMICRO) + (m * 1000); + } while (u < usec); +} diff --git a/cpu/i386/start.S b/cpu/i386/start.S index b6175b1c1d..59089ef59b 100644 --- a/cpu/i386/start.S +++ b/cpu/i386/start.S @@ -173,7 +173,41 @@ bss_fail: jmp die bss_ok: +#ifndef CONFIG_SKIP_RELOCATE_UBOOT + /* indicate progress */ + movw $0x06, %ax + movl $.progress6, %ebp + jmp show_boot_progress_asm +.progress6: + + /* copy text section to ram, size must be 4-byte aligned */ + movl $CONFIG_SYS_BL_START_RAM, %edi /* destination address */ + movl $TEXT_BASE, %esi /* source address */ + movl $_i386boot_text_size, %ecx /* number of bytes to copy */ + movl %ecx, %eax + andl $3, %eax + jz text_copy /* Already 4-byte aligned */ + subl $4, %eax /* Add extra bytes to size */ + addl %eax, %ecx +text_copy: + shrl $2, %ecx /* copy 4 byte each time */ + cld + cmpl $0, %ecx + je text_ok +text_segment: + movsl + loop text_segment + jmp text_ok +text_fail: + /* indicate (lack of) progress */ + movw $0x86, %ax + movl $.progress5a, %ebp + jmp show_boot_progress_asm +.progress5a: + jmp die +text_ok: +#endif wbinvd @@ -183,7 +217,14 @@ bss_ok: jmp show_boot_progress_asm .progress4: +#ifndef CONFIG_SKIP_RELOCATE_UBOOT + /* Jump to the RAM copy of start_i386boot */ + movl $start_i386boot, %ebp + addl $(CONFIG_SYS_BL_START_RAM - TEXT_BASE), %ebp + call *%ebp /* Enter, U-boot! */ +#else call start_i386boot /* Enter, U-boot! */ +#endif /* indicate (lack of) progress */ movw $0x85, %ax diff --git a/cpu/i386/timer.c b/cpu/i386/timer.c deleted file mode 100644 index 46db23f59c..0000000000 --- a/cpu/i386/timer.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/i8254.h> -#include <asm/ibmpc.h> - - -static volatile unsigned long system_ticks; -static int timer_init_done =0; - -static void timer_isr(void *unused) -{ - system_ticks++; -} - -unsigned long get_system_ticks(void) -{ - return system_ticks; -} - -#define TIMER0_VALUE 0x04aa /* 1kHz 1.9318MHz / 1000 */ -#define TIMER2_VALUE 0x0a8e /* 440Hz */ - -int timer_init(void) -{ - system_ticks = 0; - - irq_install_handler(0, timer_isr, NULL); - - /* initialize timer 0 and 2 - * - * Timer 0 is used to increment system_tick 1000 times/sec - * Timer 1 was used for DRAM refresh in early PC's - * Timer 2 is used to drive the speaker - * (to stasrt a beep: write 3 to port 0x61, - * to stop it again: write 0) - */ - - outb(PIT_CMD_CTR0|PIT_CMD_BOTH|PIT_CMD_MODE2, PIT_BASE + PIT_COMMAND); - outb(TIMER0_VALUE&0xff, PIT_BASE + PIT_T0); - outb(TIMER0_VALUE>>8, PIT_BASE + PIT_T0); - - outb(PIT_CMD_CTR2|PIT_CMD_BOTH|PIT_CMD_MODE3, PIT_BASE + PIT_COMMAND); - outb(TIMER2_VALUE&0xff, PIT_BASE + PIT_T2); - outb(TIMER2_VALUE>>8, PIT_BASE + PIT_T2); - - timer_init_done = 1; - - return 0; -} - - -#ifdef CONFIG_SYS_TIMER_GENERIC - -/* the unit for these is CONFIG_SYS_HZ */ - -/* FixMe: implement these */ -void reset_timer (void) -{ - system_ticks = 0; -} - -ulong get_timer (ulong base) -{ - return (system_ticks - base); -} - -void set_timer (ulong t) -{ - system_ticks = t; -} - -static u16 read_pit(void) -{ - u8 low; - outb(PIT_CMD_LATCH, PIT_BASE + PIT_COMMAND); - low = inb(PIT_BASE + PIT_T0); - return ((inb(PIT_BASE + PIT_T0) << 8) | low); -} - -/* this is not very exact */ -void udelay (unsigned long usec) -{ - int counter; - int wraps; - - if (!timer_init_done) { - return; - } - counter = read_pit(); - wraps = usec/1000; - usec = usec%1000; - - usec*=1194; - usec/=1000; - usec+=counter; - if (usec > 1194) { - usec-=1194; - wraps++; - } - - while (1) { - int new_count = read_pit(); - - if (((new_count < usec) && !wraps) || wraps < 0) { - break; - } - - if (new_count > counter) { - wraps--; - } - counter = new_count; - } - -} - -#if 0 -/* this is a version with debug output */ -void _udelay (unsigned long usec) -{ - int counter; - int wraps; - - int usec1, usec2, usec3; - int wraps1, wraps2, wraps3, wraps4; - int ctr1, ctr2, ctr3, nct1, nct2; - int i; - usec1=usec; - if (!timer_init_done) { - return; - } - counter = read_pit(); - ctr1 = counter; - wraps = usec/1000; - usec = usec%1000; - - usec2 = usec; - wraps1 = wraps; - - usec*=1194; - usec/=1000; - usec+=counter; - if (usec > 1194) { - usec-=1194; - wraps++; - } - - usec3 = usec; - wraps2 = wraps; - - ctr2 = wraps3 = nct1 = 4711; - ctr3 = wraps4 = nct2 = 4711; - i=0; - while (1) { - int new_count = read_pit(); - i++; - if ((new_count < usec && !wraps) || wraps < 0) { - break; - } - - if (new_count > counter) { - wraps--; - } - if (ctr2==4711) { - ctr2 = counter; - wraps3 = wraps; - nct1 = new_count; - } else { - ctr3 = counter; - wraps4 = wraps; - nct2 = new_count; - } - - counter = new_count; - } - - printf("udelay(%d)\n", usec1); - printf("counter %d\n", ctr1); - printf("1: wraps %d, usec %d\n", wraps1, usec2); - printf("2: wraps %d, usec %d\n", wraps2, usec3); - printf("new_count[0] %d counter %d wraps %d\n", nct1, ctr2, wraps3); - printf("new_count[%d] %d counter %d wraps %d\n", i, nct2, ctr3, wraps4); - - printf("%d %d %d %d %d\n", - read_pit(), read_pit(), read_pit(), - read_pit(), read_pit()); -} -#endif -#endif diff --git a/cpu/ixp/npe/npe.c b/cpu/ixp/npe/npe.c index 03e3bf7c16..2e6868960a 100644 --- a/cpu/ixp/npe/npe.c +++ b/cpu/ixp/npe/npe.c @@ -565,25 +565,19 @@ int npe_initialize(bd_t * bis) struct eth_device *dev; int eth_num = 0; struct npe *p_npe = NULL; + uchar enetaddr[6]; for (eth_num = 0; eth_num < CONFIG_SYS_NPE_NUMS; eth_num++) { /* See if we can actually bring up the interface, otherwise, skip it */ - switch (eth_num) { - default: /* fall through */ - case 0: - if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) { - continue; - } - break; #ifdef CONFIG_HAS_ETH1 - case 1: - if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) { + if (eth_num == 1) { + if (!eth_getenv_enetaddr("eth1addr", enetaddr)) continue; - } - break; + } else #endif - } + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + continue; /* Allocate device structure */ dev = (struct eth_device *)malloc(sizeof(*dev)); @@ -603,22 +597,14 @@ int npe_initialize(bd_t * bis) } memset(p_npe, 0, sizeof(struct npe)); - switch (eth_num) { - default: /* fall through */ - case 0: - memcpy(dev->enetaddr, bis->bi_enetaddr, 6); - p_npe->eth_id = 0; - p_npe->phy_no = CONFIG_PHY_ADDR; - break; - + p_npe->eth_id = eth_num; + memcpy(dev->enetaddr, enetaddr, 6); #ifdef CONFIG_HAS_ETH1 - case 1: - memcpy(dev->enetaddr, bis->bi_enet1addr, 6); - p_npe->eth_id = 1; + if (eth_num == 1) p_npe->phy_no = CONFIG_PHY1_ADDR; - break; + else #endif - } + p_npe->phy_no = CONFIG_PHY_ADDR; sprintf(dev->name, "NPE%d", eth_num); dev->priv = (void *)p_npe; diff --git a/cpu/mcf5227x/config.mk b/cpu/mcf5227x/config.mk index 8d60fd66bf..8eab49dff9 100644 --- a/cpu/mcf5227x/config.mk +++ b/cpu/mcf5227x/config.mk @@ -24,8 +24,8 @@ # PLATFORM_RELFLAGS += -ffixed-d7 -msep-data -ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) -PLATFORM_CPPFLAGS += -mcpu=5208 -fPIC +ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1) +PLATFORM_CPPFLAGS += -mcpu=52277 -fPIC else PLATFORM_CPPFLAGS += -m5307 -fPIC endif diff --git a/cpu/mcf523x/config.mk b/cpu/mcf523x/config.mk index 93645a31e0..fc7945451f 100644 --- a/cpu/mcf523x/config.mk +++ b/cpu/mcf523x/config.mk @@ -24,7 +24,7 @@ # PLATFORM_RELFLAGS += -ffixed-d7 -msep-data -ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) +ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1) PLATFORM_CPPFLAGS += -mcpu=5235 -fPIC else PLATFORM_CPPFLAGS += -m5307 -fPIC diff --git a/cpu/mcf52x2/config.mk b/cpu/mcf52x2/config.mk index 650e340aee..829273617b 100644 --- a/cpu/mcf52x2/config.mk +++ b/cpu/mcf52x2/config.mk @@ -34,7 +34,7 @@ is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg)) is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg)) -ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) +ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1) ifneq (,$(findstring CONFIG_M5249,$(is5249))) PLATFORM_CPPFLAGS += -mcpu=5249 diff --git a/cpu/mcf532x/config.mk b/cpu/mcf532x/config.mk index 16a0bc3264..0cb90ac4e2 100644 --- a/cpu/mcf532x/config.mk +++ b/cpu/mcf532x/config.mk @@ -24,7 +24,7 @@ # PLATFORM_RELFLAGS += -ffixed-d7 -msep-data -ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) +ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1) PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC else PLATFORM_CPPFLAGS += -m5307 -fPIC diff --git a/cpu/mcf5445x/config.mk b/cpu/mcf5445x/config.mk index 67efa07af7..b0b49f7b26 100644 --- a/cpu/mcf5445x/config.mk +++ b/cpu/mcf5445x/config.mk @@ -24,7 +24,7 @@ # PLATFORM_RELFLAGS += -ffixed-d7 -msep-data -ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) +ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1) PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC else PLATFORM_CPPFLAGS += -m5407 -fPIC diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S index d5a7f937f2..26fb2ce0cb 100644 --- a/cpu/mcf5445x/start.S +++ b/cpu/mcf5445x/start.S @@ -243,9 +243,9 @@ wait1000: nop #elif defined(CONFIG_M54451EVB) /* Issue LEMR */ - move.l #(CONFIG_SYS_SDRAM_MODE), (%a2) + move.l #(CONFIG_SYS_SDRAM_MODE), (%a1) nop - move.l #(CONFIG_SYS_SDRAM_EMOD), (%a2) + move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1) nop #endif diff --git a/cpu/mcf547x_8x/config.mk b/cpu/mcf547x_8x/config.mk index 567b281926..83102abbbb 100644 --- a/cpu/mcf547x_8x/config.mk +++ b/cpu/mcf547x_8x/config.mk @@ -24,7 +24,7 @@ # PLATFORM_RELFLAGS += -ffixed-d7 -msep-data -ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) +ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1) PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC else PLATFORM_CPPFLAGS += -m5407 -fPIC diff --git a/cpu/mcf547x_8x/cpu_init.c b/cpu/mcf547x_8x/cpu_init.c index 1ba57835e5..96a3132b78 100644 --- a/cpu/mcf547x_8x/cpu_init.c +++ b/cpu/mcf547x_8x/cpu_init.c @@ -49,14 +49,14 @@ void cpu_init_f(void) volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB; xlbarb->adrto = 0x2000; - xlbarb->datto = 0x2000; + xlbarb->datto = 0x2500; xlbarb->busto = 0x3000; - xlbarb->cfg = XARB_SR_AT | XARB_SR_DT; + xlbarb->cfg = XARB_CFG_AT | XARB_CFG_DT; /* Master Priority Enable */ - xlbarb->pri = 0; xlbarb->prien = 0xff; + xlbarb->pri = 0; #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) fbcs->csar0 = CONFIG_SYS_CS0_BASE; diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c index b9069b065e..be532afdc3 100644 --- a/cpu/mpc512x/cpu.c +++ b/cpu/mpc512x/cpu.c @@ -148,15 +148,17 @@ static void old_ft_cpu_setup(void *blob, bd_t *bd) * avoid fixing up by path because that * produces scary error messages */ + uchar enetaddr[6]; /* * old device trees have ethernet nodes with * device_type = "network" */ + eth_getenv_enetaddr("ethaddr", enetaddr); do_fixup_by_prop(blob, "device_type", "network", 8, - "local-mac-address", bd->bi_enetaddr, 6, 0); + "local-mac-address", enetaddr, 6, 0); do_fixup_by_prop(blob, "device_type", "network", 8, - "address", bd->bi_enetaddr, 6, 0); + "address", enetaddr, 6, 0); /* * old device trees have soc nodes with * device_type = "soc" diff --git a/cpu/mpc5xx/u-boot.lds b/cpu/mpc5xx/u-boot.lds index bf52179c58..cb17ca5d74 100644 --- a/cpu/mpc5xx/u-boot.lds +++ b/cpu/mpc5xx/u-boot.lds @@ -65,10 +65,8 @@ SECTIONS PROVIDE (etext = .); .rodata : { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } .fini : { *(.fini) } =0 .ctors : { *(.ctors) } diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index 9c6ab76a6f..f6258c7be6 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -28,6 +28,7 @@ #include <common.h> #include <watchdog.h> #include <command.h> +#include <net.h> #include <mpc5xxx.h> #include <netdev.h> #include <asm/io.h> @@ -121,6 +122,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4; char * cpu_path = "/cpus/" OF_CPU; #ifdef CONFIG_MPC5xxx_FEC + uchar enetaddr[6]; char * eth_path = "/" OF_SOC "/ethernet@3000"; #endif @@ -131,8 +133,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_path_u32(blob, "/" OF_SOC, "system-frequency", bd->bi_busfreq*div, 1); #ifdef CONFIG_MPC5xxx_FEC - do_fixup_by_path(blob, eth_path, "mac-address", bd->bi_enetaddr, 6, 0); - do_fixup_by_path(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0); + eth_getenv_enetaddr("ethaddr", enetaddr); + do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0); + do_fixup_by_path(blob, eth_path, "local-mac-address", enetaddr, 6, 0); #endif } #endif diff --git a/cpu/mpc5xxx/ide.c b/cpu/mpc5xxx/ide.c index df5b4acd0e..9e8f29b289 100644 --- a/cpu/mpc5xxx/ide.c +++ b/cpu/mpc5xxx/ide.c @@ -42,7 +42,7 @@ int ide_preinit (void) struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA; reg = *(vu_long *) MPC5XXX_GPS_PORT_CONFIG; -#if defined(CONFIG_TOTAL5200) +#if defined(CONFIG_SYS_ATA_CS_ON_I2C2) /* ATA cs0/1 on i2c2 clk/io */ reg = (reg & ~0x03000000ul) | 0x02000000ul; #else diff --git a/cpu/mpc5xxx/u-boot-customlayout.lds b/cpu/mpc5xxx/u-boot-customlayout.lds index f6bb858a25..9563690321 100644 --- a/cpu/mpc5xxx/u-boot-customlayout.lds +++ b/cpu/mpc5xxx/u-boot-customlayout.lds @@ -68,10 +68,8 @@ SECTIONS *(.fixup) *(.got1) . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } .fini : { *(.fini) } =0 .ctors : { *(.ctors) } diff --git a/cpu/mpc5xxx/u-boot.lds b/cpu/mpc5xxx/u-boot.lds index 8d1fa60d07..a6d4ff3888 100644 --- a/cpu/mpc5xxx/u-boot.lds +++ b/cpu/mpc5xxx/u-boot.lds @@ -57,10 +57,8 @@ SECTIONS *(.fixup) *(.got1) . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } .fini : { *(.fini) } =0 .ctors : { *(.ctors) } diff --git a/cpu/mpc8220/u-boot.lds b/cpu/mpc8220/u-boot.lds index 2a12a698df..436423c3bb 100644 --- a/cpu/mpc8220/u-boot.lds +++ b/cpu/mpc8220/u-boot.lds @@ -57,10 +57,8 @@ SECTIONS *(.fixup) *(.got1) . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } .fini : { *(.fini) } =0 .ctors : { *(.ctors) } diff --git a/cpu/mpc824x/u-boot.lds b/cpu/mpc824x/u-boot.lds index 8c7e1356d3..46f708738e 100644 --- a/cpu/mpc824x/u-boot.lds +++ b/cpu/mpc824x/u-boot.lds @@ -57,10 +57,8 @@ SECTIONS *(.fixup) *(.got1) . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } .fini : { *(.fini) } =0 .ctors : { *(.ctors) } diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c index 3ab57eb5b4..5ac02a09c0 100644 --- a/cpu/mpc8260/ether_fcc.c +++ b/cpu/mpc8260/ether_fcc.c @@ -654,7 +654,7 @@ eth_loopback_test (void) puts ("FCC Ethernet External loopback test\n"); - memcpy (NetOurEther, gd->bd->bi_enetaddr, 6); + eth_getenv_enetaddr("ethaddr", NetOurEther); /* * global initialisations for all FCC channels @@ -841,7 +841,7 @@ eth_loopback_test (void) * So, far we have only been given one Ethernet address. We use * the same address for all channels */ -#define ea gd->bd->bi_enetaddr +#define ea NetOurEther fpp->fen_paddrh = (ea[5] << 8) + ea[4]; fpp->fen_paddrm = (ea[3] << 8) + ea[2]; fpp->fen_paddrl = (ea[1] << 8) + ea[0]; diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c index 3671ef1dfb..432111df4c 100644 --- a/cpu/mpc8260/ether_scc.c +++ b/cpu/mpc8260/ether_scc.c @@ -199,6 +199,7 @@ static int sec_init(struct eth_device *dev, bd_t *bis) volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; scc_enet_t *pram_ptr; uint dpaddr; + uchar ea[6]; rxIdx = 0; txIdx = 0; @@ -261,11 +262,10 @@ static int sec_init(struct eth_device *dev, bd_t *bis) pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ -# define ea bis->bi_enetaddr + eth_getenv_enetaddr("ethaddr", ea); pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; -# undef ea pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ diff --git a/cpu/mpc8260/u-boot.lds b/cpu/mpc8260/u-boot.lds index d65a939872..b3a103dbcb 100644 --- a/cpu/mpc8260/u-boot.lds +++ b/cpu/mpc8260/u-boot.lds @@ -57,10 +57,8 @@ SECTIONS *(.fixup) *(.got1) . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } .fini : { *(.fini) } =0 .ctors : { *(.ctors) } diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 9e0a05d615..876f5c731a 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -35,6 +35,10 @@ #include <tsec.h> #include <netdev.h> #include <fsl_esdhc.h> +#ifdef CONFIG_BOOTCOUNT_LIMIT +#include <asm/immap_qe.h> +#include <asm/io.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -399,3 +403,33 @@ int cpu_mmc_init(bd_t *bis) return 0; #endif } + +#ifdef CONFIG_BOOTCOUNT_LIMIT + +#if !defined(CONFIG_MPC8360) +#error "CONFIG_BOOTCOUNT_LIMIT only for MPC8360 implemented" +#endif + +#if !defined(CONFIG_BOOTCOUNT_ADDR) +#define CONFIG_BOOTCOUNT_ADDR (0x110000 + QE_MURAM_SIZE - 2 * sizeof(unsigned long)) +#endif + +#include <asm/io.h> + +void bootcount_store (ulong a) +{ + void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR); + out_be32 (reg, a); + out_be32 (reg + 4, BOOTCOUNT_MAGIC); +} + +ulong bootcount_load (void) +{ + void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR); + + if (in_be32 (reg + 4) != BOOTCOUNT_MAGIC) + return 0; + else + return in_be32 (reg); +} +#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 491c2e5c3b..8e9c875599 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -106,7 +106,7 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | - (CONFIG_SYS_SCCR_ENCCM << SCCR_PCICM_SHIFT); + (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT); #endif #ifdef CONFIG_SYS_SCCR_PCICM diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c index f89077588f..4cc9047372 100644 --- a/cpu/mpc83xx/fdt.c +++ b/cpu/mpc83xx/fdt.c @@ -32,6 +32,20 @@ extern void ft_qe_setup(void *blob); DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_BOOTCOUNT_LIMIT) && defined(CONFIG_MPC8360) +#include <asm/immap_qe.h> + +void fdt_fixup_muram (void *blob) +{ + ulong data[2]; + + data[0] = 0; + data[1] = QE_MURAM_SIZE - 2 * sizeof(unsigned long); + do_fixup_by_path(blob, "/qe/muram/data-only", "reg", + data, sizeof (data), 0); +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; @@ -83,4 +97,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + +#if defined(CONFIG_BOOTCOUNT_LIMIT) + fdt_fixup_muram (blob); +#endif } diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c index 5fe89646c0..a42b230ff3 100644 --- a/cpu/mpc83xx/pci.c +++ b/cpu/mpc83xx/pci.c @@ -91,7 +91,7 @@ static void pci_init_bus(int bus, struct pci_region *reg) hose->regions[i].size = gd->ram_size; hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; - hose->first_busno = 0; + hose->first_busno = pci_last_busno() + 1; hose->last_busno = 0xff; pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80, @@ -227,8 +227,8 @@ void ft_pci_setup(void *blob, bd_t *bd) path = fdt_getprop(blob, nodeoffset, "pci1", NULL); if (path) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + tmp[0] = cpu_to_be32(pci_hose[1].first_busno); + tmp[1] = cpu_to_be32(pci_hose[1].last_busno); do_fixup_by_path(blob, path, "bus-range", &tmp, sizeof(tmp), 1); diff --git a/cpu/mpc83xx/pcie.c b/cpu/mpc83xx/pcie.c index 12b5f69ced..77f8906b9f 100644 --- a/cpu/mpc83xx/pcie.c +++ b/cpu/mpc83xx/pcie.c @@ -60,6 +60,9 @@ static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) #define cfg_write(val, addr, type, op) \ do { op((type *)(addr), (val)); } while (0) +#define cfg_read_err(val) do { *val = -1; } while (0) +#define cfg_write_err(val) do { } while (0) + #define PCIE_OP(rw, size, type, op) \ static int pcie_##rw##_config_##size(struct pci_controller *hose, \ pci_dev_t dev, int offset, \ @@ -68,8 +71,10 @@ static int pcie_##rw##_config_##size(struct pci_controller *hose, \ int ret; \ \ ret = mpc83xx_pcie_remap_cfg(hose, dev); \ - if (ret) \ - return ret; \ + if (ret) { \ + cfg_##rw##_err(val); \ + return ret; \ + } \ cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \ return 0; \ } @@ -86,7 +91,6 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, { extern void disable_addr_trans(void); /* start.S */ static struct pci_controller pcie_hose[PCIE_MAX_BUSES]; - static int max_bus; struct pci_controller *hose = &pcie_hose[bus]; int i; @@ -117,7 +121,7 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, hose->regions[i].size = 0x100000; hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; - hose->first_busno = max_bus; + hose->first_busno = pci_last_busno() + 1; hose->last_busno = 0xff; if (bus == 0) @@ -145,7 +149,6 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, * Hose scan. */ hose->last_busno = pci_hose_scan(hose); - max_bus = hose->last_busno + 1; } #else diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 42a4e675da..4704d2006f 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -219,7 +219,8 @@ long int spd_sdram() ddr->cs_config[0] = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr - 12) << 8 + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) | (spd.ncol_addr - 8) ); debug("\n"); debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds); @@ -231,8 +232,9 @@ long int spd_sdram() ddr->cs_config[1] = ( 1<<31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr-12) << 8 - | (spd.ncol_addr-8) ); + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) + | (spd.ncol_addr - 8) ); debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds); debug("cs1_config = 0x%08x\n",ddr->cs_config[1]); } @@ -242,7 +244,8 @@ long int spd_sdram() ddr->cs_config[2] = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr - 12) << 8 + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) | (spd.ncol_addr - 8) ); debug("\n"); debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds); @@ -254,8 +257,9 @@ long int spd_sdram() ddr->cs_config[3] = ( 1<<31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr-12) << 8 - | (spd.ncol_addr-8) ); + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) + | (spd.ncol_addr - 8) ); debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); debug("cs3_config = 0x%08x\n",ddr->cs_config[3]); } @@ -319,7 +323,20 @@ long int spd_sdram() ddrc_clk = gd->mem_clk / 1000000; effective_data_rate = 0; - if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */ + if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */ + if (spd.cas_lat & 0x08) + caslat = 3; + else + caslat = 4; + if (ddrc_clk <= 460 && ddrc_clk > 350) + effective_data_rate = 400; + else if (ddrc_clk <=350 && ddrc_clk > 280) + effective_data_rate = 333; + else if (ddrc_clk <= 280 && ddrc_clk > 230) + effective_data_rate = 266; + else + effective_data_rate = 200; + } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */ if (ddrc_clk <= 460 && ddrc_clk > 350) { /* DDR controller clk at 350~460 */ effective_data_rate = 400; /* 5ns */ @@ -466,6 +483,8 @@ long int spd_sdram() } else { twr_clk = picos_to_clk(spd.twr * 250); twtr_clk = picos_to_clk(spd.twtr * 250); + if (twtr_clk < 2) + twtr_clk = 2; } /* @@ -529,7 +548,7 @@ long int spd_sdram() if (spd.mem_type == SPD_MEMTYPE_DDR2 && (odt_wr_cfg || odt_rd_cfg) && (caslat < 4)) { - add_lat = trcd_clk - 1; + add_lat = 4 - caslat; if ((add_lat + caslat) < 4) { add_lat = 0; } @@ -566,6 +585,9 @@ long int spd_sdram() /* Convert SPD value from quarter nanos to picos. */ trtp_clk = picos_to_clk(spd.trtp * 250); + if (trtp_clk < 2) + trtp_clk = 2; + trtp_clk += add_lat; cke_min_clk = 3; /* By the book. */ four_act = picos_to_clk(37500); /* By the book. 1k pages? */ @@ -579,7 +601,9 @@ long int spd_sdram() if (spd.mem_type == SPD_MEMTYPE_DDR2) { if (effective_data_rate == 266) { cpo = 0x4; /* READ_LAT + 1/2 */ - } else if (effective_data_rate == 333 || effective_data_rate == 400) { + } else if (effective_data_rate == 333) { + cpo = 0x6; /* READ_LAT + 1 */ + } else if (effective_data_rate == 400) { cpo = 0x7; /* READ_LAT + 5/4 */ } else { /* Automatic calibration */ diff --git a/cpu/mpc83xx/u-boot.lds b/cpu/mpc83xx/u-boot.lds index 3a08f642a7..7d57ee4160 100644 --- a/cpu/mpc83xx/u-boot.lds +++ b/cpu/mpc83xx/u-boot.lds @@ -55,10 +55,8 @@ SECTIONS *(.fixup) *(.got1) . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } .fini : { *(.fini) } =0 .ctors : { *(.ctors) } diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c index 8dc2b3ac52..99c325a4ff 100644 --- a/cpu/mpc85xx/ddr-gen3.c +++ b/cpu/mpc85xx/ddr-gen3.c @@ -79,8 +79,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); - /* Do not enable the memory */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg); + /* Set, but do not enable the memory */ + temp_sdram_cfg = regs->ddr_sdram_cfg; temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); out_be32(&ddr->sdram_cfg, temp_sdram_cfg); /* diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S index 45c902e7c6..8864c37cf6 100644 --- a/cpu/mpc8xx/start.S +++ b/cpu/mpc8xx/start.S @@ -142,7 +142,7 @@ boot_warm: lis r3, IDC_DISABLE@h /* Disable data cache */ mtspr DC_CST, r3 -#if !(defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM)) +#if !defined(CONFIG_SYS_DELAYED_ICACHE) /* On IP860 and PCU E, * we cannot enable IC yet */ diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index 6fd36dea35..99b8e2f882 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -550,10 +550,12 @@ int pci_440_init (struct pci_controller *hose) out32r( PCIX0_POM0SA, 0 ); /* disable */ out32r( PCIX0_POM1SA, 0 ); /* disable */ out32r( PCIX0_POM2SA, 0 ); /* disable */ -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_440SPE) out32r( PCIX0_POM0LAL, 0x10000000 ); out32r( PCIX0_POM0LAH, 0x0000000c ); +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + out32r( PCIX0_POM0LAL, 0x20000000 ); + out32r( PCIX0_POM0LAH, 0x0000000c ); #else out32r( PCIX0_POM0LAL, 0x00000000 ); out32r( PCIX0_POM0LAH, 0x00000003 ); diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index b5d81f2e6d..577d33fead 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -321,33 +321,9 @@ cpu_init_f (void) */ int cpu_init_r (void) { -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) - bd_t *bd = gd->bd; - unsigned long reg; #if defined(CONFIG_405GP) uint pvr = get_pvr(); -#endif - - /* - * Write Ethernetaddress into on-chip register - */ - reg = 0x00000000; - reg |= bd->bi_enetaddr[0]; /* set high address */ - reg = reg << 8; - reg |= bd->bi_enetaddr[1]; - out32 (EMAC_IAH, reg); - - reg = 0x00000000; - reg |= bd->bi_enetaddr[2]; /* set low address */ - reg = reg << 8; - reg |= bd->bi_enetaddr[3]; - reg = reg << 8; - reg |= bd->bi_enetaddr[4]; - reg = reg << 8; - reg |= bd->bi_enetaddr[5]; - out32 (EMAC_IAL, reg); -#if defined(CONFIG_405GP) /* * Set edge conditioning circuitry on PPC405GPr * for compatibility to existing PPC405GP designs. @@ -356,7 +332,6 @@ int cpu_init_r (void) mtdcr(ecr, 0x60606000); } #endif /* defined(CONFIG_405GP) */ -#endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */ - return (0); + return 0; } diff --git a/cpu/pxa/interrupts.c b/cpu/pxa/interrupts.c index 40d8bf251f..2bc5c50a91 100644 --- a/cpu/pxa/interrupts.c +++ b/cpu/pxa/interrupts.c @@ -28,6 +28,7 @@ #include <common.h> #include <asm/arch/pxa-regs.h> +#include <div64.h> #ifdef CONFIG_USE_IRQ #error: interrupts not implemented yet @@ -41,6 +42,20 @@ #error "Timer frequency unknown - please config PXA CPU type" #endif +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, TIMER_FREQ_HZ); + return tick; +} + +static inline unsigned long long us_to_tick(unsigned long long us) +{ + us = us * TIMER_FREQ_HZ + 999999; + do_div(us, 1000000); + return us; +} + int interrupt_init (void) { /* nothing happens here - we don't setup any IRQs */ @@ -75,33 +90,20 @@ void reset_timer_masked (void) ulong get_timer_masked (void) { - unsigned long long ticks = get_ticks(); - - return (((ticks / TIMER_FREQ_HZ) * 1000) + - ((ticks % TIMER_FREQ_HZ) * 1000) / TIMER_FREQ_HZ); + return tick_to_time(get_ticks()); } void udelay_masked (unsigned long usec) { + unsigned long long tmp; ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= TIMER_FREQ_HZ; - tmo /= 1000; - } else { - tmo = usec * TIMER_FREQ_HZ; - tmo /= (1000*1000); - } - - endtime = get_ticks() + tmo; - - do { - ulong now = get_ticks(); - diff = endtime - now; - } while (diff >= 0); + + tmo = us_to_tick(usec); + tmp = get_ticks() + tmo; /* get current timestamp */ + + while (get_ticks() < tmp) /* loop till event */ + /*NOP*/; + } /* diff --git a/cpu/sh4/cpu.c b/cpu/sh4/cpu.c index 52b6cfd684..be410abf00 100644 --- a/cpu/sh4/cpu.c +++ b/cpu/sh4/cpu.c @@ -23,6 +23,7 @@ #include <common.h> #include <command.h> +#include <netdev.h> #include <asm/processor.h> #include <asm/cache.h> |
