1 files changed, 44 insertions, 1 deletions

diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c
index c340d569fa..21a16d97e1 100644
--- a/cpu/mpc8xxx/ddr/main.c
+++ b/cpu/mpc8xxx/ddr/main.c
@@ -164,6 +164,24 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 	}
 	if (j == 2) {
 		*memctl_interleaving = 1;
+
+		printf("\nMemory controller interleaving enabled: ");
+
+		switch (pinfo->memctl_opts[0].memctl_interleaving_mode) {
+		case FSL_DDR_CACHE_LINE_INTERLEAVING:
+			printf("Cache-line interleaving!\n");
+			break;
+		case FSL_DDR_PAGE_INTERLEAVING:
+			printf("Page interleaving!\n");
+			break;
+		case FSL_DDR_BANK_INTERLEAVING:
+			printf("Bank interleaving!\n");
+			break;
+		case FSL_DDR_SUPERBANK_INTERLEAVING:
+			printf("Super bank interleaving\n");
+		default:
+			break;
+		}
 	}
 
 	/* Check that all controllers are rank interleaving. */
@@ -175,10 +193,30 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 	}
 	if (j == 2) {
 		*rank_interleaving = 1;
+
+		printf("Bank(chip-select) interleaving enabled: ");
+
+		switch (pinfo->memctl_opts[0].ba_intlv_ctl &
+						FSL_DDR_CS0_CS1_CS2_CS3) {
+		case FSL_DDR_CS0_CS1_CS2_CS3:
+			printf("CS0+CS1+CS2+CS3\n");
+			break;
+		case FSL_DDR_CS0_CS1:
+			printf("CS0+CS1\n");
+			break;
+		case FSL_DDR_CS2_CS3:
+			printf("CS2+CS3\n");
+			break;
+		case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+			printf("CS0+CS1 and CS2+CS3\n");
+		default:
+			break;
+		}
 	}
 
 	if (*memctl_interleaving) {
 		phys_addr_t addr;
+		phys_size_t total_mem_per_ctlr = 0;
 
 		/*
 		 * If interleaving between memory controllers,
@@ -197,14 +235,18 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 
 		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 			addr = 0;
+			pinfo->common_timing_params[i].base_address =
+						(phys_addr_t)addr;
 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 				unsigned long long cap
 					= pinfo->dimm_params[i][j].capacity;
 
 				pinfo->dimm_params[i][j].base_address = addr;
 				addr += (phys_addr_t)(cap >> dbw_cap_adj[i]);
+				total_mem_per_ctlr += cap >> dbw_cap_adj[i];
 			}
 		}
+		pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
 	} else {
 		/*
 		 * Simple linear assignment if memory
@@ -314,7 +356,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
 			 */
 			populate_memctl_options(
 					timing_params[i].all_DIMMs_registered,
-					&pinfo->memctl_opts[i], i);
+					&pinfo->memctl_opts[i],
+					pinfo->dimm_params[i], i);
 		}
 
 	case STEP_ASSIGN_ADDRESSES: