diff options
Diffstat (limited to 'board/ti')
| -rw-r--r-- | board/ti/am335x/board.c | 40 | ||||
| -rw-r--r-- | board/ti/am43xx/board.c | 355 | ||||
| -rw-r--r-- | board/ti/am43xx/board.h | 36 | ||||
| -rw-r--r-- | board/ti/am43xx/mux.c | 35 | ||||
| -rw-r--r-- | board/ti/dra7xx/evm.c | 8 | ||||
| -rw-r--r-- | board/ti/ti814x/evm.c | 4 | ||||
| -rw-r--r-- | board/ti/ti816x/evm.c | 12 |
7 files changed, 470 insertions, 20 deletions
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 33693e4ead..57217688d6 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -426,6 +426,38 @@ void set_mux_conf_regs(void) enable_board_pin_mux(&header); } +const struct ctrl_ioregs ioregs_evmsk = { + .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, +}; + +const struct ctrl_ioregs ioregs_bonelt = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +const struct ctrl_ioregs ioregs_evm15 = { + .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, +}; + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, +}; + void sdram_init(void) { __maybe_unused struct am335x_baseboard_id header; @@ -443,18 +475,18 @@ void sdram_init(void) } if (board_is_evm_sk(&header)) - config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, + config_ddr(303, &ioregs_evmsk, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); else if (board_is_bone_lt(&header)) - config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE, + config_ddr(400, &ioregs_bonelt, &ddr3_beagleblack_data, &ddr3_beagleblack_cmd_ctrl_data, &ddr3_beagleblack_emif_reg_data, 0); else if (board_is_evm_15_or_later(&header)) - config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, + config_ddr(303, &ioregs_evm15, &ddr3_evm_data, &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); else - config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, + config_ddr(266, &ioregs, &ddr2_data, &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); } #endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 51b257683d..ed87cd97b0 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -9,22 +9,326 @@ */ #include <common.h> +#include <i2c.h> +#include <asm/errno.h> #include <spl.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mux.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/gpio.h> +#include <asm/emif.h> #include "board.h" DECLARE_GLOBAL_DATA_PTR; +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(struct am43xx_board_id *header) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + printf("Could not probe the EEPROM at 0x%x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return -ENODEV; + } + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, + sizeof(struct am43xx_board_id))) { + printf("Could not read the EEPROM\n"); + return -EIO; + } + + if (header->magic != 0xEE3355AA) { + /* + * read the eeprom using i2c again, + * but use only a 1 byte address + */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(struct am43xx_board_id))) { + printf("Could not read the EEPROM at 0x%x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return -EIO; + } + + if (header->magic != 0xEE3355AA) { + printf("Incorrect magic number (0x%x) in EEPROM\n", + header->magic); + return -EINVAL; + } + } + + strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name)); + am43xx_board_name[sizeof(header->name)] = 0; + + return 0; +} + #ifdef CONFIG_SPL_BUILD -const struct dpll_params dpll_ddr = { - -1, -1, -1, -1, -1, -1, -1}; +#define NUM_OPPS 6 + +const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { + { /* 19.2 MHz */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */ + {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 24 MHz */ + {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 25 MHz */ + {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 26 MHz */ + {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ + }, +}; + +const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { + {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ + {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ + {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ +}; + +const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { + {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */ + {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */ + {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params epos_evm_dpll_ddr = { + 266, 24, 1, -1, 1, -1, -1}; + +const struct dpll_params gp_evm_dpll_ddr = { + 400, 23, 1, -1, 1, -1, -1}; + +const struct ctrl_ioregs ioregs_lpddr2 = { + .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0x1, +}; + +const struct emif_regs emif_regs_lpddr2 = { + .sdram_config = 0x808012BA, + .ref_ctrl = 0x0000040D, + .sdram_tim1 = 0xEA86B411, + .sdram_tim2 = 0x103A094A, + .sdram_tim3 = 0x0F6BA37F, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x0, + .emif_rd_wr_lvl_ctl = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E084006, + .emif_rd_wr_exec_thresh = 0x00000405, + .emif_ddr_ext_phy_ctrl_1 = 0x04010040, + .emif_ddr_ext_phy_ctrl_2 = 0x00500050, + .emif_ddr_ext_phy_ctrl_3 = 0x00500050, + .emif_ddr_ext_phy_ctrl_4 = 0x00500050, + .emif_ddr_ext_phy_ctrl_5 = 0x00500050 +}; + +const u32 ext_phy_ctrl_const_base_lpddr2[] = { + 0x00500050, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40001000, + 0x08102040 +}; + +const struct ctrl_ioregs ioregs_ddr3 = { + .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0x0043, +}; + +const struct emif_regs ddr3_emif_regs_400Mhz = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E084008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00400040, + .emif_ddr_ext_phy_ctrl_3 = 0x00400040, + .emif_ddr_ext_phy_ctrl_4 = 0x00400040, + .emif_ddr_ext_phy_ctrl_5 = 0x00400040, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x0, + .emif_rd_wr_lvl_ctl = 0x0, + .emif_rd_wr_exec_thresh = 0x00000405 +}; + +const u32 ext_phy_ctrl_const_base_ddr3[] = { + 0x00400040, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00340034, + 0x00340034, + 0x00340034, + 0x00340034, + 0x00340034, + 0x0, + 0x0, + 0x40000000, + 0x08102040 +}; + +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) +{ + if (board_is_eposevm()) { + *regs = ext_phy_ctrl_const_base_lpddr2; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); + } else if (board_is_gpevm()) { + *regs = ext_phy_ctrl_const_base_ddr3; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); + } + + return; +} const struct dpll_params *get_dpll_ddr_params(void) { - return &dpll_ddr; + struct am43xx_board_id header; + + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + if (board_is_eposevm()) + return &epos_evm_dpll_ddr; + else if (board_is_gpevm()) + return &gp_evm_dpll_ddr; + + puts(" Board not supported\n"); + return NULL; +} + +/* + * get_sys_clk_index : returns the index of the sys_clk read from + * ctrl status register. This value is either + * read from efuse or sysboot pins. + */ +static u32 get_sys_clk_index(void) +{ + struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; + u32 ind = readl(&ctrl->statusreg), src; + + src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT; + if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */ + return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >> + CTRL_CRYSTAL_FREQ_SELECTION_SHIFT); + else /* Value read from SYS BOOT pins */ + return ((ind & CTRL_SYSBOOT_15_14_MASK) >> + CTRL_SYSBOOT_15_14_SHIFT); +} + +/* + * get_opp_offset: + * Returns the index for safest OPP of the device to boot. + * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. + * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. + * This data is read from dev_attribute register which is e-fused. + * A'1' in bit indicates OPP disabled and not available, a '0' indicates + * OPP available. Lowest OPP starts with min_off. So returning the + * bit with rightmost '0'. + */ +static int get_opp_offset(int max_off, int min_off) +{ + struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; + int opp = readl(&ctrl->dev_attr), offset, i; + + for (i = max_off; i >= min_off; i--) { + offset = opp & (1 << i); + if (!offset) + return i; + } + + return min_off; +} + +const struct dpll_params *get_dpll_mpu_params(void) +{ + int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); + u32 ind = get_sys_clk_index(); + + return &dpll_mpu[ind][opp]; +} + +const struct dpll_params *get_dpll_core_params(void) +{ + int ind = get_sys_clk_index(); + + return &dpll_core[ind]; +} + +const struct dpll_params *get_dpll_per_params(void) +{ + int ind = get_sys_clk_index(); + + return &dpll_per[ind]; } void set_uart_mux_conf(void) @@ -37,14 +341,41 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); } +static void enable_vtt_regulator(void) +{ + u32 temp; + + /* enable module */ + writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO0_BASE + OMAP_GPIO_CTRL); + + /* enable output for GPIO0_22 */ + writel(GPIO_SETDATAOUT(GPIO_22), + AM33XX_GPIO0_BASE + OMAP_GPIO_SETDATAOUT); + temp = readl(AM33XX_GPIO0_BASE + OMAP_GPIO_OE); + temp = temp & ~(GPIO_OE_ENABLE(GPIO_22)); + writel(temp, AM33XX_GPIO0_BASE + OMAP_GPIO_OE); +} + void sdram_init(void) { + /* + * EPOS EVM has 1GB LPDDR2 connected to EMIF. + * GP EMV has 1GB DDR3 connected to EMIF + * along with VTT regulator. + */ + if (board_is_eposevm()) { + config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); + } else if (board_is_gpevm()) { + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400Mhz, 0); + } } #endif int board_init(void) { - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; return 0; } @@ -52,6 +383,22 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + char safe_string[HDR_NAME_LEN + 1]; + struct am43xx_board_id header; + + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + /* Now set variables based on the header. */ + strncpy(safe_string, (char *)header.name, sizeof(header.name)); + safe_string[sizeof(header.name)] = 0; + setenv("board_name", safe_string); + + strncpy(safe_string, (char *)header.version, sizeof(header.version)); + safe_string[sizeof(header.version)] = 0; + setenv("board_rev", safe_string); +#endif return 0; } #endif diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 8ca098b82a..091162ee20 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -12,6 +12,42 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +#include <asm/arch/omap.h> + +static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START; + +/* + * TI AM437x EVMs define a system EEPROM that defines certain sub-fields. + * We use these fields to in turn see what board we are on, and what + * that might require us to set or not set. + */ +#define HDR_NO_OF_MAC_ADDR 3 +#define HDR_ETH_ALEN 6 +#define HDR_NAME_LEN 8 + +#define DEV_ATTR_MAX_OFFSET 5 +#define DEV_ATTR_MIN_OFFSET 0 + +struct am43xx_board_id { + unsigned int magic; + char name[HDR_NAME_LEN]; + char version[4]; + char serial[12]; + char config[32]; + char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; +}; + +static inline int board_is_eposevm(void) +{ + return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN); +} + +static inline int board_is_gpevm(void) +{ + return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN); +} + void enable_uart0_pin_mux(void); void enable_board_pin_mux(void); +void enable_i2c0_pin_mux(void); #endif diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 700e9a76ad..810b1941db 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -12,8 +12,29 @@ #include "board.h" static struct module_pin_mux uart0_pin_mux[] = { - {OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)}, /* UART0_RXD */ - {OFFSET(uart0_txd), (MODE(0))}, /* UART0_TXD */ + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CMD */ + {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux gpio0_22_pin_mux[] = { + {OFFSET(ddr_ba2), (MODE(9) | PULLUP_EN)}, /* GPIO0_22 */ {-1}, }; @@ -24,4 +45,14 @@ void enable_uart0_pin_mux(void) void enable_board_pin_mux(void) { + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(i2c0_pin_mux); + + if (board_is_gpevm()) + configure_module_pin_mux(gpio0_22_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); } diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 9ae88c57a4..1b60b8f672 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -202,12 +202,12 @@ int board_eth_init(bd_t *bis) /* try reading mac address from efuse */ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); - mac_addr[0] = mac_hi & 0xFF; + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = mac_lo & 0xFF; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; mac_addr[4] = (mac_lo & 0xFF00) >> 8; - mac_addr[5] = (mac_lo & 0xFF0000) >> 16; + mac_addr[5] = mac_lo & 0xFF; if (!getenv("ethaddr")) { printf("<ethaddr> not set. Validating first E-fuse MAC\n"); diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index 0b76a77905..140ad7103a 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -95,9 +95,9 @@ void sdram_init(void) { config_dmm(&evm_lisa_map_regs); - config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, + config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif0_regs, 0); - config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, + config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif1_regs, 1); } #endif diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c index a53859e52e..b6bf16236f 100644 --- a/board/ti/ti816x/evm.c +++ b/board/ti/ti816x/evm.c @@ -191,22 +191,26 @@ void sdram_init(void) if (CONFIG_TI816X_USE_EMIF0) { ddr2_emif0_regs.emif_ddr_phy_ctlr_1 = (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); - config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0); + config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, + 0); } if (CONFIG_TI816X_USE_EMIF1) { ddr2_emif1_regs.emif_ddr_phy_ctlr_1 = (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); - config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1); + config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, + 1); } #endif #ifdef CONFIG_TI816X_EVM_DDR3 if (CONFIG_TI816X_USE_EMIF0) - config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0); + config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, + 0); if (CONFIG_TI816X_USE_EMIF1) - config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, 1); + config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, + 1); #endif } #endif /* CONFIG_SPL_BUILD */ |
