diff options
Diffstat (limited to 'board/freescale/p1_p2_rdb')
| -rw-r--r-- | board/freescale/p1_p2_rdb/config.mk | 31 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/ddr.c | 47 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/p1_p2_rdb.c | 66 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/tlb.c | 22 |
4 files changed, 68 insertions, 98 deletions
diff --git a/board/freescale/p1_p2_rdb/config.mk b/board/freescale/p1_p2_rdb/config.mk deleted file mode 100644 index 076980498c..0000000000 --- a/board/freescale/p1_p2_rdb/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# Copyright 2009, 2011 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# p1_p2rdb board -# - -ifndef NAND_SPL -ifeq ($(CONFIG_NAND), y) -LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds -endif -endif diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index e54fde2530..71c60888ac 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009, 2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -30,14 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num); - -#define DATARATE_400MHZ 400000000 -#define DATARATE_533MHZ 533333333 -#define DATARATE_667MHZ 666666666 -#define DATARATE_800MHZ 800000000 - #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 @@ -82,13 +74,13 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100 #define CONFIG_SYS_DDR_TIMING_3_800 0x00040000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x55770802 +#define CONFIG_SYS_DDR_TIMING_0_800 0x00770802 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 #define CONFIG_SYS_DDR_MODE_1_800 0x00040852 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = { .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, @@ -204,38 +196,47 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { phys_size_t fixed_sdram (void) { - sys_info_t sysinfo; char buf[32]; fsl_ddr_cfg_regs_t ddr_cfg_regs; size_t ddr_size; struct cpu_type *cpu; + ulong ddr_freq, ddr_freq_mhz; + + cpu = gd->cpu; + /* P1020 and it's derivatives support max 32bit DDR width */ + if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || + cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { + ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); + } else { + ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + } +#if defined(CONFIG_SYS_RAMBOOT) + return ddr_size; +#endif + ddr_freq = get_ddr_freq(0); + ddr_freq_mhz = ddr_freq / 1000000; - get_sys_info(&sysinfo); printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, sysinfo.freqDDRBus)); + strmhz(buf, ddr_freq)); - if(sysinfo.freqDDRBus <= DATARATE_400MHZ) + if(ddr_freq_mhz <= 400) memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs)); - else if(sysinfo.freqDDRBus <= DATARATE_533MHZ) + else if(ddr_freq_mhz <= 533) memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs)); - else if(sysinfo.freqDDRBus <= DATARATE_667MHZ) + else if(ddr_freq_mhz <= 667) memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs)); - else if(sysinfo.freqDDRBus <= DATARATE_800MHZ) + else if(ddr_freq_mhz <= 800) memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs)); else panic("Unsupported DDR data rate %s MT/s data rate\n", - strmhz(buf, sysinfo.freqDDRBus)); + strmhz(buf, ddr_freq)); - cpu = gd->cpu; /* P1020 and it's derivatives support max 32bit DDR width */ if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE; ddr_cfg_regs.cs[0].bnds = 0x0000001F; - ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); } - else - ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 078094200f..307c3e2564 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -35,6 +35,7 @@ #include <vsc7385.h> #include <netdev.h> #include <rtc.h> +#include <i2c.h> DECLARE_GLOBAL_DATA_PTR; @@ -54,38 +55,25 @@ DECLARE_GLOBAL_DATA_PTR; #define SYSCLK_MASK 0x00200000 #define BOARDREV_MASK 0x10100000 -#define BOARDREV_B 0x10100000 #define BOARDREV_C 0x00100000 #define BOARDREV_D 0x00000000 #define SYSCLK_66 66666666 -#define SYSCLK_50 50000000 #define SYSCLK_100 100000000 unsigned long get_board_sys_clk(ulong dummy) { volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - u32 val_gpdat, sysclk_gpio, board_rev_gpio; + u32 val_gpdat, sysclk_gpio; val_gpdat = in_be32(&pgpio->gpdat); sysclk_gpio = val_gpdat & SYSCLK_MASK; - board_rev_gpio = val_gpdat & BOARDREV_MASK; - if (board_rev_gpio == BOARDREV_C) { - if(sysclk_gpio == 0) - return SYSCLK_66; - else - return SYSCLK_100; - } else if (board_rev_gpio == BOARDREV_B) { - if(sysclk_gpio == 0) - return SYSCLK_66; - else - return SYSCLK_50; - } else if (board_rev_gpio == BOARDREV_D) { - if(sysclk_gpio == 0) - return SYSCLK_66; - else - return SYSCLK_100; - } + + if(sysclk_gpio == 0) + return SYSCLK_66; + else + return SYSCLK_100; + return 0; } @@ -112,8 +100,6 @@ int checkboard (void) board_rev_gpio = val_gpdat & BOARDREV_MASK; if (board_rev_gpio == BOARDREV_C) board_rev = 'C'; - else if (board_rev_gpio == BOARDREV_B) - board_rev = 'B'; else if (board_rev_gpio == BOARDREV_D) board_rev = 'D'; else @@ -121,6 +107,9 @@ int checkboard (void) cpu = gd->cpu; printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev); +#ifdef CONFIG_PHYS_64BIT + puts ("(36-bit addrmap) \n"); +#endif setbits_be32(&pgpio->gpdir, GPIO_DIR); /* @@ -142,6 +131,30 @@ int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + unsigned int orig_bus = i2c_get_bus_num(); + u8 i2c_data; + + i2c_set_bus_num(1); + if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, + 1, &i2c_data, sizeof(i2c_data)) == 0) { + if (i2c_data & 0x2) + puts("NOR Flash Bank : Secondary\n"); + else + puts("NOR Flash Bank : Primary\n"); + + if (i2c_data & 0x1) { + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); + puts("SD/MMC : 8-bit Mode\n"); + puts("eSPI : Disabled\n"); + } else { + puts("SD/MMC : 4-bit Mode\n"); + puts("eSPI : Enabled\n"); + } + } else { + puts("Failed reading I2C Chip 0x18 on bus 1\n"); + } + i2c_set_bus_num(orig_bus); /* * Remap Boot flash region to caching-inhibited @@ -229,12 +242,3 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); } #endif - -#ifdef CONFIG_MP -extern void cpu_mp_lmb_reserve(struct lmb *lmb); - -void board_lmb_reserve(struct lmb *lmb) -{ - cpu_mp_lmb_reserve(lmb); -} -#endif diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index a46b1b5670..1847935a73 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -25,19 +25,20 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -80,15 +81,10 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_256K, 1), +#if defined(CONFIG_SYS_RAMBOOT) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_1G, 1) #endif }; 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