diff options
Diffstat (limited to 'board/esd/pci405/pci405.c')
| -rw-r--r-- | board/esd/pci405/pci405.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index 56184caa8f..04bc569ead 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -67,7 +67,7 @@ const unsigned char fpgadata[] = int board_revision(void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; unsigned long value; /* @@ -77,8 +77,8 @@ int board_revision(void) /* * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03000000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200); udelay(1000); /* wait some time before reading input */ @@ -87,7 +87,7 @@ int board_revision(void) /* * Restore GPIO settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); switch (value) { case 0x00100200: @@ -133,7 +133,7 @@ unsigned long fpga_init_state(void) int board_early_init_f (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board) @@ -166,18 +166,18 @@ int board_early_init_f (void) /* * Setup GPIO pins (IRQ4/GPIO21 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00008000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000); /* * Setup GPIO pins (CS6+CS7 as GPIO) */ - mtdcr(cntrl0, cntrl0Reg | 0x00300000); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } @@ -282,11 +282,11 @@ int misc_init_r (void) #define PCI0_BRDGOPT1 0x4a pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20); -#define plb0_acr 0x87 +#define PLB0_ACR 0x87 /* * Enable fairness and high bus utilization */ - mtdcr(plb0_acr, 0x98000000); + mtdcr(PLB0_ACR, 0x98000000); free(dst); return (0); @@ -313,14 +313,14 @@ int checkboard (void) printf(" (Rev 1.%ld", gd->board_type); if (gd->board_type >= 2) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; unsigned long value; /* * Setup GPIO pins (Trace/GPIO1 to GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg & ~0x08000000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000); udelay(1000); /* wait some time before reading input */ |
